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2023-03-29vc/amd/fsp/mendocino/FspmUpd: Update UDP structure for MDN-FSPChris.Wang
Update UPD structure to align with MDN-FSP. BUG=b:271704149 BRANCH=none TEST=Build/Boot to Chrome OS Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ie4021cebb57e3ec22191486aafd9099eec0fbd99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-03-27vc/amd/fsp/mendocino:Add fch_usb_3_port_force_gen1 tp AGESA FSP-M UPDPatrick Huang
To add fch_usb_3_port_force_gen1 parameter to force usb3 port to gen1 BUG=b:273841155 BRANCH=None TEST=Build Change-Id: I7560abb9a5fda6af3c2814f8b26c92925d8c17f4 Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-27soc/amd/mendocino: Add UPDs for DPTC current limitsPatrick Huang
Add UPD vrm_current_limit_mA, vrm_maximum_current_limit_mA, vrm_soc_current_limit_mA for DPTC. Make sure UPD parameterare are set to be aligned. BUG=b:245942343 BRANCH=none TEST=confirm the UPD parameters has been set correspondingly with the FSP UPD. Change-Id: Iacf0ce0d51d4c8698ec1ae7e810fd00574deeadb Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73875 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-20soc/amd/mendocino: Consume fsp misc_data hobJason Glenesk
Provide support function to query fsp misc_data hob and return smu reported power and thermal limit. BUG=b:253301653 TEST=Use get_amd_smu_reported_tdp(&tdp) values match what FSP placed in the hob. Change-Id: I9f0d8cdd616726c5a714e99504b83b0126dd273b Signed-off-by: Jason Glenesk <jason.glenesk@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73747 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-13soc/amd/mendocino: Add svc_write_postcode call instead of stubMartin Roth
To assist in debugging, add a way for PSP_verstage to send postcodes to the system. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I22e45e26f599a0b4f0b781e9b97fccb68e2e5cc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-05vc/amd/pi: Fix "No such file or directory"Elyes Haouas
Fix: cc1: error: src/vendorcode/amd/pi/00670F00: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/binaryPI: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Include: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Common: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU/Family: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch/Common: No such file or directory [-Werror=missing-include-dirs] Change-Id: I745f4fc421c91c413fe0d3155d3494ed9704eeb6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-17treewide: Fix old-style declarationsElyes Haouas
Replace old style declaration "const static" with "static const". This to enable "Wold-style-declaration" command option. Change-Id: I757632befed1854f422daaf4dfea58281b16e2f5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15soc/amd/mendocino: PSP_INCLUDES_HSPKarthikeyan Ramasubramanian
Select HSP config to indicate that the SoC includes Hardware Security Processor. This will allow PSP verstage to get and report the HSP state. BUG=None TEST=Build Skyrim BIOS image and boot to ChromeOS on Skyrim. Verify that HSP is reported during the boot sequence. Change-Id: I22446c2bd6202529367da040c09449e6b26f9d7a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15vc/amd/*,soc/amd/*: Add SVC call to get HSP Secure StateKarthikeyan Ramasubramanian
Add an SVC call to get the state of Hardware Security Processor (HSP) in AMD SoCs. This SVC call will be used from PSP verstage to get and report HSP state. BUG=b:198711349 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the HSP state is read and reported in the firmware logs. Change-Id: I7fe3363d308a80cc09e6bdadd8d0bb1d67f7d2bf Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71207 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/amd: Change Morgana codename to PhoenixMartin Roth
Now that the next generation of APUs is officially announced, we can unmask morgana. The chip formerly known as Morgana is actually Phoenix. Surprise! This patch just changes the name across the entire codebase. Note that the fw.cfg file will stay pointing to the 3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is updated. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimizationChris.Wang
Add the UPD dxio_tx_vboost_enable for PCIe optimization. It will impact the PCIe signal integrity, need to double-confirm the SI result after enabling this setting. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-03vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directoryElyes Haouas
Fix: CC romstage/mainboard/amd/pademelon/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/amd/gardenia/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/google/kahlee/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/google/kahlee/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-21vc/amd,soc/amd/mendocino: Add SVC_CMD_GET_PREV_BOOT_STATUSKarthikeyan Ramasubramanian
Add an SVC command to get the previous boot status. If there is any pre-x86 boot failure in the previous boot cycle, PSP stores it in warm reset persistent register and triggers a warm reset. PSP verstage on the subsequent boot gets the previous boot status and reports any failure to the vboot before a FW slot is selected. BUG=b:242825052 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Trigger a failure scenario by corrupting certain firmware blobs and observe that PSP reports the failure boot status. On a normal boot, observed that PSP reports successful boot. Change-Id: I440deee560b72c80491bfdd7fda38a1c3a4299e5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70381 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12vc/amd/fsp/glinda/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5db2587ff74432a0ce1805d8d7ae76d650693eea Reviewed-on: https://review.coreboot.org/c/coreboot/+/70506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-12vc/amd/fsp/morgana/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Also make sure that the address of the lcl_usb_phy struct is located below the 4GB boundary, so that the truncation to 32 bits won't result in pointing to a different memory location than intended. In this error case, which I don't expect to happen, print an error and write 0 to mcfg->usb_phy_ptr so that the FSP will use its default values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1394aa6ef5f401e0c7bdd4861f1e28ae46e56e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70505 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08vc/amd/fsp/cezanne/FspmUpd: don't use pointers for usb_phy configurationFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I81f3a38344f91cecb4fe5431ed211834e5ed599c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69897 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08vc/amd/fsp/mendocino/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I419fef73d2881e323487bc7fe641b2ac4041cb17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-19vc/amd/fsp/glinda/platform_descriptors.h: Update for glindaFred Reitberger
Update definitions on glinda used by birman. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I03065011581489b5345c16e225edc341e1d7811c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-19vc/amd/fsp/morgana/platform_descriptors.h: Update for morganaFred Reitberger
Update definitions to match morgana FSP. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ic893526789c05a298965702114d4a814466a5742 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-11vc/amd/fsp/mendocino: Update FSP UPD signatures to MNDCNOMartin Roth
The FSPM and FSPS UPD signatures hadn't been updated from their cezanne origins. Change them to MNDCNO_M/S. BUG=b:240573135 TEST=Build & boot, see new signature in boot log. Change-Id: I9e4fcf7a9bf802aaba88f3dccf6da064c5686e96 Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-11-07vendorcode/amd/ccx_cppc_data.h: Fix header guardArthur Heymans
Change-Id: I027c3aa7bb206112107ee120cf6f9854e37c5636 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69230 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07sb/amd: Remove dropped platformsArthur Heymans
This code is now unused by any platform. Change-Id: I60afbde6ead70f0c887866fc351b4a6a15a89287 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69120 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07cpu/amd/agesa: Remove leftover codeArthur Heymans
Now that all agesa CPUs are removed this code is unused. Change-Id: If0c082bbdb09457e3876962fa75725add11cb67c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69118 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07vendorcode/amd/agesa: Drop unused common codeArthur Heymans
No platform uses this. Change-Id: If32a4de7ef263f1d4f7ab7a36751ad9dcf52dc7e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69127 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07vendorcode/amd/agesa/family16: Drop unused platformArthur Heymans
This platform use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: Ie2ef5424c3ebe75ff98361639a0f9980101c1141 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69126 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07{cpu/nb}/amd/family16: Remove platformArthur Heymans
This platform use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I589f30ccf81b6cf243ac7cbf8320a3f830649ad8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69117 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07vendorcode/amd/agesa/fam15tn: Drop unused platformArthur Heymans
This platform use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I749cf33fad12bb9bc5cd5d682df2652107d60a0f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69125 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07vendorcode/amd/agesa/fam14: Remove dropped platformArthur Heymans
This platform use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I9dd3ce763418ff767acd0c55be26a998df77081b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69124 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-27vc/amd/fsp: Add Glinda directoryMartin Roth
Copied from Morgana - Needs to be updated. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id3175e6e6b5c7210b7c29f30e21e5a66f234c52a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-22vc/amd/fsp: Get rid of last "sabrina" referenceMartin Roth
We still had a lingering reference to the old sabrina codename in the vendorcode directory. Searching through the code now, the only places the sabrina codename is seen is in the release notes, as is proper. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I41762880b45a85ce7cd4210b8ce623076d874c06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21mb/google/skyrim/port_descriptors: update DDI for MDN and ChausieJason Nien
Add two new types for MDN DDI descriptor BUG=b:228284940 TEST=Normal boot and S0i3 cycles Signed-off-by: Jason Nien <finaljason@gmail.com> Change-Id: I02793f032f9855dac202a5aca8666c26426d6cb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66847 Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-10-08vc/amd/fsp: Add Morgana FSP vendorcodeMartin Roth
Initial commit of the FSP-specific code for the Morgana SoC. This is just an initial framework and still needs to be updated to match the Morgana FSP. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ic53c59404f96c73c55eb2648113c5ced26d6e20c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-10-08vc/amd/fsp: Make common directoryMartin Roth
The common directory is for files that shouldn't change, or shouldn't change much between platforms. These will be removed from other directories and used in upcoming commits. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I37ed98a67b066598fdebcc5b034e64dc639fda7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-09-23soc/amd/mendocino: Add svc_set_fw_hash_tableKarthikeyan Ramasubramanian
Add new PSP svc call to pass psp firmware hash table to the PSP. psp_verstage will verify hash table and then pass them to the PSP. The PSP will check if signed firmware contents match these hashes. This will prevent anyone replacing signed firmware in the RW region. BUG=b:203597980 TEST=Build and boot to OS in Skyrim. Change-Id: I512d359967eae925098973e90250111d6f59dd39 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67259 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24vc/amd/fsp/mendocino: Update DMI_T17_MEMORY_TYPEMatt DeVillier
Synchronize with AGESA/AgesaModulePkg/Include/MemDmi.h. Add/correct values for DDR5, LPDDR5, LPDDR5X. BUG=b:239000826 TEST=Build and verify with other patches in train Change-Id: I127f21bfe2dfcd7794eb543185ea3fb362ff3914 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-13vc/amd/fsp/cezanne,mendocino: add FSP CCX CPPC HOB GUID and structFelix Held
To generate a complete _CPC ACPI object, coreboot needs the minimal and nominal core speed values which are specific to the CPU and not only the CPU family. Since this is done by an undocumented mechanism, FSP has to do this and puts the information we need into a HOB. This adds the HOB GUID and the structure of the HOB data. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Change-Id: Ibf338c32de367a3fd57695873da1625338fa196d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66549 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11treewide: Rename Sabrina to MendocinoJon Murphy
'Mendocino' was an embargoed name and could previously not be used in references to Skyrim. coreboot has references to sabrina both in directory structure and in files. This will make life difficult for people looking for Mendocino support in the long term. The code name should be replaced with "mendocino". BUG=b:239072117 TEST=Builds Cq-Depend: chromium:3764023 Cq-Depend: chromium:3763392 Cq-Depend: chrome-internal:4876777 Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-01Revert "UPSTREAM: soc/amd/sabrina,vc/amd/fsp/sabrina: Add UART support for ↵Karthikeyan Ramasubramanian
Sabrina" This reverts commit 78261e308de5361b2ff045091e8fb18cad2a5035. Reason for revert: Now that PSP supports a soft fuse flag to toggle the verstage serial logs, prevent PSP verstage from writing to the UART. BUG=None TEST=Build and boot to OS in Skyrim with PSP verstage. Ensure that PSP verstage logs are not seen twice in the console. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7ef2d585c320ea5903197939136dd2049a71af95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-20vc/amd/fsp/sabrin/bl_uapp_header: Add SoC FW ID at the right offsetKarthikeyan Ramasubramanian
SoC FW ID needs to be populated at offset 0x58 and 0x59 in the PSP header. BUG=b:217414563 TEST=Build Skyrim BIOS image and ensure that PSP verstage is getting loaded. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ibe7b26aea0567e5337ee3e6e9447aa3944c55f5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-06soc/amd/sabrina,vc/amd/fsp/sabrina: Add UART support for SabrinaJon Murphy
Sabrina previously didn't support UART mapping in psp verstage. Now that it has been enabled, add the relevant uart code here. BUG=b:218709292 TEST=Set serial soft fuse, boot to kernel, check logs Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I591fa69b6e722929839babfff62e9d56c68e1112 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65532 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-08vc/amd/agesa/f15tn: Declare `value` as constant in `GnbRegisterWriteTNDump()`Paul Menzel
Do not discard the const qualifier in `GnbRegisterWriteTNDump()` to fix the compiler warning below. CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.o In file included from src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:53: src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c: In function 'GnbRegisterWriteTN': src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:836:57: error: passing argument 3 of 'GnbRegisterWriteTNDump' discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers] 836 | GnbRegisterWriteTNDump (RegisterSpaceType, Address, Value); | ^~~~~ src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h:68:35: note: in definition of macro 'GNB_DEBUG_CODE' 68 | #define GNB_DEBUG_CODE(Code) Code | ^~~~ src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:86:33: note: expected 'VOID *' {aka 'void *'} but argument is of type 'const VOID *' {aka 'const void *'} 86 | IN VOID *Value | ~~~~~~~~~~~~~~~~~~~~~^~~~~ CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.o CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.o CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.o CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.o CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.o src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c: At top level: cc1: note: unrecognized command-line option '-Wno-pragma-pack' may have been intended to silence earlier diagnostics cc1: all warnings being treated as errors Found-by: gcc (Debian 11.3.0-3) 11.3.0 Change-Id: I2039cf66030030458bd247a31adc0621b9d033e6 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-07Replace some ENV_ROMSTAGE with ENV_RAMINITKyösti Mälkki
With a combined bootblock+romstage ENV_ROMSTAGE might no longer evaluate true. Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-28vendorcode/amd/agesa: Remove -fno-zero-initialized-in-bssArthur Heymans
There are zero-initialized arrays within AGESA that were previously not declared with CONST qualifier. Without this flag, such arrays would have consumed valuable CAR space in romstage. After adding CONST qualifiers these arrays have actually moved to .rodata and removing the flag does not add anything to .bss. TEST: see that BUILD_TIMELESS=1 results in the same binary. Change-Id: I5b91deb1bf1b64bd9c88dc311db4e0b36df86c18 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28vendorcode/amd/agesa/fam16kb: Fix improper use of .dataArthur Heymans
AGESA has a lot of code in the .data section which is for initialized data, that in fact should be .rodata. This adds the 'CONST' keyword everywhere it is needed. TEST: See in the .elf file (e.g. using readelf) that there is nothing in .data section. Change-Id: Ie8817434ee0bc6c195eabe090f195512c0043ae5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-05-28vendorcode/amd/agesa/f14: Fix improper use of .dataArthur Heymans
AGESA has a lot of code in the .data section which is for initialized data, that in fact should be .rodata. This adds the 'CONST' keyword everywhere it is needed. TEST: See in the .elf file (e.g. using readelf) that there is nothing in .data section. Change-Id: I657d09f05070f5a88a4a162872c961db869a8df3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-05-28vendorcode/amd/agesa/f15tn: Fix all improper use of .dataArthur Heymans
AGESA has a lot of code in the .data section which is for initialized data, that in fact should be .rodata. This adds the 'CONST' keyword everywhere it is needed. TEST: See in the .elf file (e.g. using readelf) that there is nothing in .data section. Change-Id: I9593c24f764319f66a64715d91175f64edf10608 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-05-20vc/amd/fsp/sabrina: Update PSP header to set the SOC FW IDJon Murphy
Update the PSP header to set the SOC FW ID to 0x0149 for this platform BUG=b:217414563 TEST=Build and verify header is set correctly Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ic604ec96560c2d4d89c48c4a27528c5cfe4ca7e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16soc/amd/cezanne/fsp_m_params: add defines for FSP USB struct versionFelix Held
Add and use defines instead of magic values in fsp_m_params.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie0e33eb0af5310ab4610ea8951688464c4960260 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64126 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.h: Correct SPD_PERSONALITY_BYTEElyes Haouas
Regarding Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules DDR3 - Document Release 6 (JEDEC Standard No. 21-C Page 4.1.2.11 – 69) memory buffer personality bytes is located at bytes 102 ~ 116. Change-Id: I7d225fb5e80b537b4c0ce1c23b7a4524e9109a7b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-12vc/amd/fsp/sabrina/UsbUpd: update USB settings structure to match FSPFelix Held
This file started as a copy from Cezanne. Sabrina has less USB ports than Cezanne. Also the struct definition of fch_usb2_phy has changed and FSP_USB_STRUCT_MINOR_VERSION is also updated. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1ef2b62373b178d729b3230d0d8539986cc631ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/64129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-12soc/amd/sabrina/fsp_m_params: add defines for FSP USB struct versionFelix Held
Add and use defines instead of magic values in fsp_m_params.c. The values will be updated to match the Sabrina FSP in a follow-up commit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I91da9e9d2b95e169dd73153766f24cf8afbfa4ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/64128 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-11amd/*/gcccar.inc: Replace local declarationsArthur Heymans
Although useful to declare local symbols inside macros clang does not support them. Using the \@ symbol which increments each time the macro is used we can do the same. With BUILD_TIMELESS=1 the binaries don't change and do build with GCC so nothing is lost here. Change-Id: I01054e2bdcb63810b21eb51b46bdc6e1bd999516 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-11vendorcode/amd/cimx/sb900: Drop codeArthur Heymans
No mainboard is using this code. Change-Id: I4374360c211593a8468b6226f3d1729885b533e0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-11amd/fam15tn/gcccar.inc: Fix msr access with clangArthur Heymans
Change-Id: I21bebd475dce373a77626d2e78a0ab10678ea8b6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-11amd/f15tn/gcccar.inc: Fix macro with ClangArthur Heymans
Change-Id: I0d95ac9d548e410a81188307cc92f77224baea0e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-04-24soc/amd/sabrina/psp_verstage: Unify SVC IDKarthikeyan Ramasubramanian
In Sabrina, PSP verstage uses a unified SVC call ID with sub-commands. Update the SVC calls for Sabrina to pass the SVC_VERSTAGE_CMD (command ID) with individual subcommands and the corresponding parameters. BUG=b:220848545, b:217414563 TEST=Build the Skyrim BIOS image with PSP verstage enabled. Change-Id: I56be51aa1dfb00e5f0945014600de2bbbec289db Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-27vc/amd/fsp/sabrina/platform_descriptor: update DXIO lane mapping tableFelix Held
Sabrina only supports PCIe and no SATA or 10 GBit/s ethernet on its DXIO lanes. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib5aa3abf21e20bbe846f1acfdc2755e97eca1e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63121 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-25vendorcode/amd/pi: Fix building with clangArthur Heymans
Change-Id: I82913de07acc13af2f5f2c67853e112fb3c66319 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-25amd/cimx/sb800: Fix building with clangArthur Heymans
These are all set but unused variable problems. Change-Id: I40aaa1d1cdd90731a23142f1f7a0f67a45915f25 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-25vendorcode/amd/agesa: Add CFLAGS required by CLANGArthur Heymans
Vendorcode is messy so instead of trying to fix the warnings thrown by clang ignore them on AGESA platforms. Change-Id: I378571c2b7272901761c786c6daec0a403155d4c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-11soc/amd/common/fsp: check fsp image revisionJulian Schroeder
Check if FSP binary and coreboot FSP structures (fspmupd.h) match sufficiently. A change in minor number denotes less critical changes or additions to the FSP API that still allow for the boot process to proceed. A change of the AMD image revision major number will halt boot. The Fspmupd.h header now defines IMAGE_REVISION_ macros for AMD Picasso, Cezanne and Sabrina APUs. BUG=b:184650244 TEST=build, boot and check fsp image revision info. Example: FSP major = 1 FSP minor = 0 FSP revision = 5 FSP build = 0 Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I0fbf9413b0cf3e6093ee9c61ff692ff78ebefebc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-07vc/amd/cezanne: Add support to map UARTsRaul E Rangel
This will allow coreboot to directly write to the UART controller. BUG=b:215599230 TEST=Try mapping the uart on guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibd346cec2994e612f2901bb91d572982ce2ed5e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-02soc/amd/cezanne,vc/cezanne: Implement svc_write_postcodeRaul E Rangel
This will allow verstage to write post codes. BUG=b:215425753 TEST=Boot guybrush and verify PSP post codes are printed 22-01-31 15:12:03.214 (S3->S0) 22-01-31 15:12:03.214 03 04 0f 0e f0 f1 f2 01 10 a0 a2 <--new Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61522 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-01psp_verstage: add new svc for cezanneKangheui Won
Add svc_set_platform_bootmode svc to cezanne. PSP will use this information to select proper widevine keybox. BUG=b:211058864 TEST=build guybrush Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-26vc/amd/agesa: fix out-of-bounds readJason Nien
Fix the out-of-bounds read issue found by Coverity. TEST=none Signed-off-by: Jason Nien <finaljason@gmail.com> Change-Id: I01e134cb6b025bf7cb5030cd9378297d7f6df509 Reported-by: Coverity (CID:1376956) Reviewed-on: https://review.coreboot.org/c/coreboot/+/58803 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-25soc/amd/cezanne: FSP: Add UPD entry for eDP tuningZheng Bao
The FSP gets these values from the UPD and sets the internal values. The document about eDP tuning is attached in issue tracker of this ticket, at the issue tracker b/203061533#comment6. BUG=b:203061533 Cq-Depend: chrome-internal:4303901 Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-25vc/amd/fsp/sabrina: add as a copy of vc/amd/fsp/cezanneFelix Held
The AMD Sabrina SoC will be using the FSP driver to call into the corresponding FSP binary to do its part of for the silicon initialization, so we need an initial set of FSP headers for the AMD Sabrina SoC code to build. Since the FSP interface for this SoC won't be too different from the Cezanne FSP interface, we'll start with a copy of the Cezanne FSP headers and update/replace them as soon as the proper FSP headers for Sabrina will be available. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib3bf50598efe60673b81cf99da491866fb5dc121 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-30Cezanne FSP wrapper: Sync with PI 1.0.0.5Zheng Bao
New PI 1.0.0.5 has more data in HOB of DMI, which has been uploaded to google internal repo. The dismatched size of HOB causes the wrong data tranfer. So the coreboot also need to change. BUG=b:204732649 Change-Id: Id95c37a0d7027d75afddf9d7528ff41ae3a347f5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11vc/amd/fsp/cezanne: Add UPD fsp_owns_pcie_resets to FSP-M for CezanneMatt Papageorge
Update UPD to include option for FSP to de-assert PCIe reset GPIOs as specified in the DXIO descriptors. This change requires FSP version 1.0.4 revision 2 otherwise setting this value does affect any FSP behavior. BUG=b:199780346 TEST=Verify toggling this value is reflected in FSP Cq-Depend: chrome-internal:4170351 Change-Id: I0dee05fb0a650f026c2f09581117fa7fb5f6a90a Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-27soc/amd/cezanne, vc/amd/fsp/*: Add support for CCP DMA SVC callKarthikeyan Ramasubramanian
Add support to access the boot device from PSP through Crypto Co-Processor (CCP) DMA. Implement a SVC call to use CCP DMA on SoCs where it is supported and a stub on SoCs where it is not supported. This provides an improved performance while accessing the boot device and reduces the boot time by ~45 ms. BUG=b:194990811 TEST=Build and boot to OS in guybrush. Perform cold and warm reboot cycling for 250 iterations. Change-Id: I02b94a842190ac4dcf45ff2d846b8665f06a9c75 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-20vc/amd/sb800: Fix out of bounds shiftPaul Menzel
Fix the two issues below. SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/PCILIB.c:49:18 ubsan: unrecoverable error. SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/PCILIB.c:66:18 ubsan: unrecoverable error. Found by: UBSAN Change-Id: Id42e62d35f59793bad10998f14422ab7fb4fc029 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-09-20vc/amd/agesa/Kconfig: Move SPD options out of choiceAngel Pons
The Kconfig options for custom SPD values aren't supposed to be part of the choice block. Change-Id: I12eb1012f94000b14e5d7f1e5123dddf69ac1a94 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57717 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-22AGESA f15tn: Fix building IDS tracing supportAngel Pons
Also add a config file to ensure the code gets build-tested. Change-Id: I530eccd2a194bc79de5ee354d98260d93423cd5b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53986 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-22AGESA f15tn: Hook up IDS options to KconfigAngel Pons
IDS (Integrated Debug Services) options are meant to be enabled when one wants to debug AGESA. Since they are compile-time options, using Kconfig is the logical choice. Currently, none of the options builds. Tested with BUILD_TIMELESS=1 without adding the configuration options into the binary, and Asus A88XM-E does not change. Change-Id: I465627c19c9856e58ca94aa0efedbddb6baaf3f6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-08-22AGESA f15tn: Factor out common OptionsIds.hAngel Pons
Subsequent commits will add Kconfig options to configure IDS. Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical. Change-Id: I861762280b274566ce14969a30e2e0c98e120a69 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-08-22AGESA f15tn: Drop `IDSOPT_ASSERT_ENABLED`Angel Pons
The `ASSERT` macro is already defined in `src/include/assert.h`, and AGESA's definition is never used. On Asus A88XM-E, toggling the value of the `IDSOPT_ASSERT_ENABLED` macro does not change the resulting binary when using reproducible builds. Attempting to use AGESA's definition of the `ASSERT` macro results in build errors: In file included from src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c:56: src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c: In function 'GetType4Type7Info': src/vendorcode/amd/agesa/f15tn/Include/Ids.h:371:33: error: statement with no effect [-Werror=unused-value] #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE)); Given that coreboot's definition of `ASSERT` is more useful, drop AGESA's broken definition and the useless `IDSOPT_ASSERT_ENABLED` macro. Also remove the `IdsAssert` function, as it is no longer used anywhere. Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical. Change-Id: Ia4e5dbfd3d2e5cec979b8b16fbc11d1ca8a0661e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-21soc/amd/cezanne: enable crypto in psp_verstageKangheui Won
Enable RSA and SHA for cezanne since support has been added to the PSP. Also picasso and cezanne have different enums definitions for hash algorithm, so split that out into chipset.c. BUG=b:187906425 TEST=boot guybrush, check cbmem -t and the logs Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I725b0cac801ac0429f362a83aa58a8b9de158550 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-12vc/amd/sb800: Cast to UINT32 for shift out of bounds fixPaul Menzel
It’s defined as `unsigned char`. SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/SBCMN.c:643:53 ubsan: unrecoverable error. Found-by: UBSAN Change-Id: I0c5fa16bce5b68ed3b48bb17eae6d81af894b688 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-12vc/amd/sb800: Cast variable to 32-bit before shiftPaul Menzel
SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/Gpp.c:151:61 ubsan: unrecoverable error. Found-by: UBSAN Change-Id: I6cbef2fa9806fd6da67031ca01bb25205013b478 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-12vc/amd/sb800: SBCMN: Cast to 32-bit before shiftPaul Menzel
SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/SBCMN.c:486:57 ubsan: unrecoverable error. Found-by: UBSAN Change-Id: Id05b96f1f4cf4a1cf8283db22e10ab8df833406d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51286 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21vc/amd/fsp/cezanne/FspmUpd: add hda_enable UPDFelix Held
This UPD to enable/disable the non-graphics HD audio controller was added in FSP build version 1.0.3.1, so sync the header file in coreboot with this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I15eee45dc5d12a420eb688eaa5879c92b6d1b2c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-13soc/amd/cezanne: Supply SMBIOS/DMI Type 17 dataNikolai Vyssotski
Enable generation of DMI Type 17 data on Cezanne. BUG=b:184124605 TEST="dmidecode --type 17" in OS on Majolica Change-Id: Iaa89ee1ce6efa0280f17a443e07571a1190873a6 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-06-07soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOBNikolai Vyssotski
EDK2 mandates HOB to be in increments of qword (8). This HOB has 13 elements which causes it be padded with 4 bytes of garbage. This results in coreboot failing intermittently with invalid data. Add "number of entries" field to specify the number of valid entries in the table. BUG=b:190153208 Cq-depend: chrome-internal:3889619 TEST=verify HOB is present and correct size (13) is reported Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55237 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07cezanne/psp_verstage: add reset/timer svcKangheui Won
The new cezanne PSP release added support for these svcs. So add those functionality back to cezanne psp_verstage. BUG=b:187906425 Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-26vc/amd/pi/00630F01: Remove unused directory and codeMichał Żygowski
No board currently uses AMD PI 00630F01 so remove it. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3f990e44e0f769219a6f80cf1369f6a3c94b3509 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53994 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26soc/amd/cezanne: add support for the changed AMD FSP API for USB PHYJulian Schroeder
The AMD FSP is using a new structure for USB and USB C phy settings. This patch removes old, unused structures, adds the new one and enables the devicetree interface for it. Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Reviewed-on: https://review.coreboot.org/c/coreboot/+/54065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-21soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driverFelix Held
commit ce0e2a014009390c4527e064efb59260ef4d3a3b (drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region) adds a mechanism to reserve the BERT region inside the coreboot code, so we can get rid of the workaround to reserve it in the FSP and return the location in a HOB. mcfg->bert_size defaults to 0 which makes the FSP not generate the corresponding HOB, but that field is planned to be removed at least on Cezanne, so don't explicitly set it to 0. BUG=b:169934025 TEST=BERT table that gets generated in a follow-up patch for Picasso points to expected BERT region and Linux is able to access, decode and display it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaca89b47793bf9982181560f026459a18e7db134 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52584 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-12vc/amd/pi/00660F01: Remove unused code and directoryMichał Żygowski
This is some leftover omitted during 00660F01 removal, since corresponding CPU and northbridge code is not present in the tree already. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib7ccbc088766b5a4f59c47bd48790c6a2af8ca61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-10src: Drop "This file is part of the coreboot project" linesAngel Pons
Commit 6b5bc77c9b22c398262ff3f4dae3e14904c57366 (treewide: Remove "this file is part of" lines) removed most of them, but missed some files. Change-Id: Ib8e7ab26a74b52f86d91faeba77df3331531763f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-05-06vc/amd/fsp/cezanne: Add AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUIDRaul E Rangel
This HOB describes the PCI routing table. It will be consumed by coreboot to generate the _PRT ACPI object. BUG=b:184766519, b:184766197 TEST=Build guybrush Cq-Depend: chrome-internal:3794981 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib790004b88dfaf7671534f657c7735f6718114db Reviewed-on: https://review.coreboot.org/c/coreboot/+/52869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-05vc/amd/fsp/cezanne/FspGuids: add AMD_FSP_ACPI_ALIB_HOB_GUIDFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I531c8e8d0ee2aa72b51cba59e09e7a7d253da4f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-02vendorcode: add code for cezanne psp_verstageKangheui Won
These are mostly copied from picasso code with exception for bl_syscall_public.h. For some SVCs svc number and/or prototype has been changed. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6b431fdbf34fca2747833980ae53c06244905f93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-30amd/cezanne: Add telemetry setting to UPDChris Wang
Add telemetry setting to UPD, the value comes from the SDLE testing. BUG=b:182754399 TEST=Build & Boot guybrush Cq-Depend: chrome-internal:3787638 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I9dd3643e9c582a41192130901935eef321b2c67e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52733 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-27vc/amd/agesa/f15tn/Config/PlatformInstall.h: enable the AMD CPB featureMike Banon
Enable the AMD Turbo Core a.k.a. AMD Core Performance Boost (CPB) feature [1] for f15tn boards - like it's already done for f14 and f16kb. According to CB:51394 [2] it improves the performance of Lenovo G505S by up to 50%, and is unlikely to cause regressions for the other boards. [1] https://en.wikipedia.org/wiki/AMD_Turbo_Core [2] https://review.coreboot.org/c/coreboot/+/51394 Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I1eaa8ff3953c492e8f9431d7b4a09b86e0ef77a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-26amd/cezanne: Add slow_ppt_time & thermctl_limit to UPDMartin Roth
These values will be added in the upcoming STAPM configuration update. BUG=b:185209734 TEST=Build & Boot guybrush Cq-Depend: chrome-internal:3780259 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I2a6835c16badfe505e3c33b356ca671766cd6972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: chris wang <Chris.Wang@amd.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26src/vendorcode/amd/fsp/picasso: Add HDMI 2.0 Disable setting section of ↵Patrick Huang
FspmUpd.h This change adds HDMI 2.0 Disable setting BUG=b:179170193 BRANCH=none TEST=Build; Verify the UPD was passed to system integrated table Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: Ie00389074f3718a23440c41ae0b116455aa8b603 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2021-04-26vc/amd/fsp/cezanne:Add s0i_enable upd controlJason Glenesk
Add upd to enable S0i3 in fsp. BUG=b:178728116 TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the sleep state configuration from the mainboard. Cq-Depend: chrome-internal:3777391 Change-Id: I01759caa4d72e284b2b960634f89c6a2ab1dad57 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-20vc/amd/fsp/cezanne: update SMU setting section of FspmUpd.hFelix Held
There was a bug in the UPDs for STAPM settings that required one UPD field to be extended from 8 to 32 bits, so this patch is a breaking change to the binary layout, but since the UPD struct fields for the SMU SoC power and performance tuning parameters aren't populated by the coreboot code yet and we added some padding after each logical section in the UPD, this isn't expected to cause too much trouble; the only thing that is required is that a very recent build of the FSP binaries need to be used in combination with the new coreboot code that will populate the struct fields in follow-up patches. BUG=b:182297189 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If39aaf64e8e1b4c0426f22ce8ed07707c2a31e61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-07vc/amd/fsp/cezanne/FspmUpd: use arrays for DXIO/DDI descriptorsFelix Held
This allows coreboot to easily iterate over the descriptors. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2ecb3b543f90b8c6a957794f0c55b0ba5c72d59d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>