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2018-01-05soc/amd/common: load post-memory AGESA as rmoduleAaron Durbin
Now that the AGESA binary is split into two sections load the post-memory AGESA binary into ram. It needs to be an rmdoule so that it can be relocated into ram. agesawrapper_amdinitenv() entry CBFS: 'VBOOT' located CBFS at [10000:cfd40) CBFS: Locating 'AGESA_POST_MEM' CBFS: Found @ offset 875c0 size 11c5e Decompressing stage AGESA_POST_MEM @ 0xc757ffc0 (183452 bytes) Loading module at c7580000 with entry c7580000. filesize: 0x2bafc memsize: 0x2bb0d Processing 1112 relocs. Offset value of 0xc7780000 AGESA call 00020001 using c75818fe AGESA call 00020003 using c75818fe Fch OEM config in INIT ENV Done agesawrapper_amdinitenv() returned AGESA_SUCCESS BUG=b:68141063,b:70714803 TEST=Booted kahlee. Change-Id: Ic0454e0d6909cb34ae8be2f4f221152532754d61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-05soc/amd/common: Allow AGESA file split for pre- and post-memoryJustin TerAvest
By splitting the binary files for platform initialization, the post-memory code can be modified to stop executing in place (--xip). This change creates two separate sections in CBFS for AGESA and loads the appropriate file at the correct stage. BUG=b:68141063 TEST=Booted kahlee with split agesa enabled. Change-Id: I2fa423df164037bc3738476fd2a34522df279e34 Signed-off-by: Justin TerAvest <teravest@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-13vc/amd/pi/0067F00: add option to add AGESA binary PI as stageAaron Durbin
Stage addition to CBFS allows relocation to happen on the fly. Take advantage of that by adding AGESA binary PI as a stage file so that each instance will be relocated properly within CBFS. Without this patch Chrome OS having multiple CBFS instances just redirects the AGESA calls back into RO which is inappropriate. BUG=b:65442265,b:68141063 TEST=Enabled AGESA_BINARY_PI_AS_STAGE and used ELF file. Booted and noted each instance in Chrome OS build was relocated. Change-Id: Ic0141bc6436a30f855148ff205f28ac9bce30043 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-12vc/amd/pi/00670F00: fix #include paths to only use <amdblocks/header.h>Aaron Durbin
Ensure that soc/amd/common/blocks/include is the only #include path for the AMD common code. This removes the duplicate soc/amd/common include as well using the correct #include header in AGESA.c. BUG=b:69262110 Change-Id: I50d85b28514fd905df415f0cc052b9924ee4e741 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-12soc/amd/common: Move Agesa related headersRichard Spiegel
Move AGESA related headers in soc/amd/common to soc/amd/common/block/include/amdblocks. BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, headers moved). Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-11vc/amd/pi/00670F00/binaryPI: cache the AGESA dispatcherAaron Durbin
Instead of repeatedly walking cbfs for the AGESA blob and parsing it cache the resulting dispatcher value. There's only one dispatcher table so use it. The resulting change is that this work is done one time per stage. BUG=b:70401101 TEST=Booted and noted only one lookup per stage. Change-Id: Iaa4aecc384108d66d7c68fc5fb9ac1c3f40da905 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22789 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2017-11-22vendorcode/amd/pi/00670F00: Halt build if headers aren't wrappedMartin Roth
Make sure that AGESA headers don't get pulled directly into coreboot files again. BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee; Include AGESA.h into files verify that the build fails. Change-Id: I8d6d94872ebf76a9df2850ed0452cf6b1a446ffd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-22vendorcode/amd/pi/00670F00: Remove direct AGESA header includesMartin Roth
Update amdlib to pull in the AGESA headers through agesa_headers.h BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee Change-Id: I3a2a2fde9738a9fe7a0b55cb91c29416cdc227a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21vendorcode/amd/pi/00670F00: Clean up makefileMartin Roth
- Remove unnecessary cflags, exports, and variables - Don't include AGESA cflags in the entire build - Reformat build target BUG=b:69220826 TEST=Build Change-Id: I60cb20a3849439cb808f5d3919588853e9c8c734 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19vendorcode/amd/pi/00670F00: Remove dependency on amd/include dirMartin Roth
Copy the two headers used by the Stoney BinaryPI implementation into the 00670F00 directory so that any changes that are made to them don't affect other platforms. BUG=b:67299330 TEST=Build Change-Id: I5d37fac72871f2617c4be45c151741436cbfce96 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19vendorcode/amd/pi/00670F00: Remove cpuFamilyTranslation.cMartin Roth
The file Proc/CPU/cpuFamilyTranslation.c isn't being included into the build, so it's obviously not needed. BUG=b:69220826 TEST=Build Change-Id: Id244d110b4f15e1d6af6c701f62e2f05d7eb289a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-16vendorcode/amd/pi/00670F00: Get rid of filecodes, replace filecode.hMartin Roth
coreboot doesn't need AGESA's version of Filecode.h. Some of the files that have been copied from AGESA include the header, so we can't get rid of it completely yet. - Remove includes from files that weren't copied from the AGESA source. - Remove FILECODE definitions from coreboot source. BUG=B:69220826 TEST=Build Gardenia; Build & boot Kahlee. Change-Id: If16feafc12dedeb90363826b62ea7513e54277f4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-16vendorcode/amd/pi: Create stoney version of amdlibMartin Roth
Copy the vendorcode/amd/pi/Lib directory into 00670F00 directory and update the 00670F00 Makefile to use it instead of using the common version. This allows changes to stoney without affecting the rest of the AMD binary PI platforms. BUG=b:67299330 TEST=Build Gardenia; Build & boot kahlee Change-Id: I2fe4303f882938e9d917a3001476213f49426455 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-16vendorcode/amd/pi: Split stoney PI into its own MakefileMartin Roth
- Copy vendorcode/amd/pi makefile to 00670F00 directory - Remove all stoney references from the vendorcode/amd/pi makefile - Remove all non-stoney references from 00670F00 Makefile - Remove directories that don't exist from 00670F00 Makefile -- Proc/CPU/Feature -- Proc/Fch/Kern -- Proc/Fch/Kern/KernImc BUG=b:67299330 TEST=Build Gardenia; Build & boot kahlee Change-Id: I34690cfc3b1c4508d25d7cf062fcb9aea5945634 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14AMD Stoney Ridge: Add agesa_headers.hMartin Roth
- Create header files for the stoneyridge PI that pulls in AGESA pi headers and encloses them in #pragma pack push/pop to keep the '#pragma pack(1)' in Porting.h from leaking. - Add that header to agesawrapper.h, replacing AGESA.h and Porting.h Following patches will update the coreboot code to use only agesawrapper.h to pull in the AGESA headers. BUG=b:66818758 TEST=Build tested Change-Id: Ib7d76811c1270ec7ef71266d84f3960919b792d4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11vendorcode/amd/pi/00670f00: Set ModuleIdentifier to be 8 bytesMartin Roth
ModuleIdentifier must be 8 bytes. Every other location else that uses this value explicityly defines it as 8 bytes. If it's initialized here to less than 8 bytes, it gets passed to those other locations with garbage at the end and fails to load the AGESA binary. TEST=Build & boot Kahlee BUG=B:69165234 Change-Id: I11fc90748f49782e2b16ee5326aee17cfe92d0bc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03vendorcode/amd/pi/00670F00: remove unused headersMartin Roth
These header files are not used, so remove them. BUG=b:68812513 TEST=Build Change-Id: Ib43fc544186f7b46ecf9b318b9edcf008f2d08dc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20vendorcode/amd/pi/00670F00: Remove S3 restore functionsMartin Roth
These functions are not currently used, and were not in the original AGESA source code drop. The structs involved here were marked "private" in AGESA headerfiles and should not be exposed. They could be handled as anonymous structs and required allocation size is communicated by other means. BUG=b:64766233 TEST=Build in cros tree and upstream coreboot, with old headers and updated headers. Change-Id: Iec346205470150257fd9d09131d54231b321740b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-19src/vendorcode/amd: Use AR variable in MakefilesMartin Roth
Change-Id: I5158f1bcc18eb5b15f310d0cf50fb787c12317c8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-03vc/amd/pi/00670F00: Remove HeapXXBuffer functionsMartin Roth
The HeapAllocateBuffer and HEAPDeallocateBuffer functions are not used in Stoney Ridge, so get rid of them. Change-Id: I716d5c8957ced52c25fd501697111b1b0b263467 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-03vendorcode/amd/pi: Put libagesa build all in libagesa directoryMartin Roth
Half the files were being placed in build/agesa and half in build/libagesa. Change-Id: Ied69dafffe2eb3354bd430789e098a1cb1d40551 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-28amd/stoneyridge: Drop FieldAcccessorsKyösti Mälkki
It was either SAGE or AMD AES who implemented these for binaryPI, and it is not part of the documented AGESA API. My conclusions of these are: AmdGetValue() returns values from build-time configuration, these may not reflect the actual run-time configuration as there are OEM customization hooks to implement overrides. AmdSetValue() in __PRE_RAM__ will fail, as configuration data is const. Also AmdSetValue() in ramstage may fail, if said configuration data has already been evaluated. Semamtics of these calls are unusable unless one also has access to PI source to make exact decision on when they can be called. Remove these now that stoneyridge does not actually require them. Change-Id: I3379a75ce3b9448c17ef00eb16d3193c296626cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-27soc/amd/stoneyridge: Revert CAR teardown wbinvdMarshall Dawson
Change the cache-as-ram teardown to use invd instead of wbinvd. Save the return and recover the call's return address in chipset_teardown_car. CAR teardown had been modified to use wbinvd to send CAR contents to DRAM backing prior to teardown. This allowed CAR variables, stack, and local variables to be preserved while running the AMD_DISABLE_STACK macro. Using the wbinvd instruction has the side effect of sending all dirty cache contents to DRAM and not only our CAR data. This would likely cause corruption, e.g. during S3 resume. Stoney Ridge now uses a postcar stage and this is no longer a requirement. BUG=b:64768556 Change-Id: I8e6bcb3947f508b1db1a42fd0714bba70074837a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20967 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-26AGESA: Implement POSTCAR_STAGEKyösti Mälkki
Move all boards that have moved away from AGESA_LEGACY_WRAPPER or BINARYPI_LEGACY_WRAPPER to use POSTCAR_STAGE. We use POSTCAR_STAGE as a conditional in CAR teardown to tell our MTRR setup is prepared such that invalidation without writeback is a valid operation. Change-Id: I3f4e2170054bdb84c72d2f7c956f8d51a6d7f0ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02binaryPI: Introduce BINARYPI_LEGACY_WRAPPER and its counterpartKyösti Mälkki
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA via functions in agesawrapper.c file. The approach implemented there makes it very inconvenient to do board-specific customisation or present common platform-specific features. Seems like it also causes assertion errors on AGESA side. The flag is applied here to all boards and then individually removed one at a time, as things get tested. New method is not to call AGESA internal functions directly, but via the dispatcher. AGESA call parameters are routed to hooks in both platform and board -directories, to allow for easy capture or modification as needed. For each AGESA dispatcher call made, eventlog entries are replayed to the console log. Also relocations of AGESA heap that took place are recorded. New method is expected to be compatible with binaryPI. Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCKMarshall Dawson
Add dedicated CAR setup and teardown functions and Kconfig options to force their inclusion into the build. The .S files are mostly duplicated code from the old cache_as_ram.inc file. The .S files use global proc names in anticipation for use with the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE. Move the mainboard romstage functionality into the soc directory and change the function name to be compatible with the call from assembly_entry.S. Drop the BIST check like other devices. Move InitReset and InitEarly to bootblock. These AGESA entry points set some default settings, and release/recapture the AP cores. There are currently some early dependencies on InitReset. Future work should include: * Pull the necessary functionality from InitReset into bootblock * Move InitReset and InitEarly to car_stage_entry() and out of bootblock - Add a mechanism for the BSP to give the APs an address to call and skip most of bootblock and verstage (when available) (1) - Reunify BiosCallOuts.c and OemCustomize.c (1) During the InitReset call, the BSP enables the APs by setting core enable bits in F18F0x1DC and APs begin fetching/executing from the reset vector. The BSP waits for all APs to also reach InitReset, where they enter an endless loop. The BSP sends a command to them to execute a HLT instruction and the BSP eventually returns from InitReset. The goal would be to preserve this process but prevent APs from rerunning early code. Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-15vendorcode/amd/pi: Tidy up gcccar.incKyösti Mälkki
Remove register preservations that are not required and fix comments about register usage accordingly. Change-Id: Ibc9ed982ac55e947c100739250db122033348a82 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20576 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-15vendorcode/amd/pi: Clarify CAR disableMarc Jones
Clean up commentary on AMD_DISABLE_STACK to be clear that it does a wbinvd to preserve coreboot CBMEM and value of car_migrated. Change-Id: I1265ed3d1bdf4b22f1a56f68bc53e18cfadc44b2 Signed-off-by: Marc Jones <marcj303@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-12binaryPI: Drop non-soc stoneyridge treesKyösti Mälkki
These sources are no longer part of build-tests and transition to soc/ appears to be completed. Change-Id: I9bc2212f44d79c795e5b8f6d62b6ee3c42de779a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-07-11binaryPI: Define AGESA blob in CBFS as Kconfig stringKyösti Mälkki
Change-Id: I0f78cb275ecad732f81c609564a0640f03d2559e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-07-03vendorcode/amd/pi: Update AGESA_CFLAGSMartin Roth
* Split the existing cflags to a second line to stay under 80 characters * Correctly identify the libagesa "Stage" by adding the __LIBAGESA__ define to the files when they're compiled. This matches stage defines such as __BOOTBLOCK__, __ROMSTAGE__, and __RAMSTAGE__. This is needed to have printk actually show console information on whatever interface the user has selected, such as the serial port, speaker, SPI rom, or something else that hasn't been thought of yet. Change-Id: I2a64414491130275ba06e5bd76e0b01e450174e8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-03vendorcode/amd/pi/Lib/amdlib.c: remove StdHeader referencesMartin Roth
Nothing in the amdlib.c file actually uses the StdHeader structure, so remove the asserts verifying that it's not null, and remove references to it from calls. For now, I've left it in the parameters for the functions for compatibility, but we might want to remove these at some point as well. Change-Id: Ib13e9209c8119fdcc3720470aaa9dcdbde6ac388 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-27vendorcode/amd: Unify Porting.h across all targetsStefan Reinauer
This requires to also unify the calling convention for AGESA functions from AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr) to AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr) On systems running 32bit x86 code this will not make a difference as UINTN is uintptr_t which is 32bit on these machines. Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-26vendorcode/amd: Drop multiple copies of gcc-intrin.hStefan Reinauer
Change-Id: Ifc6a0638c03fa5f3e1007a844e56dfa6f4c71d7e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-26vendorcode/amd: Unify gcc-intrin.hStefan Reinauer
Most of these functions go unused most of the time, but in order to not keep several copies around, let's make sure we are using the same file everywhere first. Change-Id: Ie121e67f3663410fd2860b7d619e8a679c57caba Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-26soc/amd/stoneyridge: Add northbridge supportMarc Jones
Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc/amd/stoneyridge: Add CPU filesMarc Jones
Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. This is the second patch in the process of converting Stoney Ridge to soc/. Changes: - update Kconfig and Makefiles - update vendorcode/amd for new soc/ path Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc: Add AMD Stoney Ridge southbridge codeMarc Jones
Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-06northbridge/amd/stoney: Add FT4 packageMarshall Dawson
Add package options to the CPU Kconfig that may be selected by the mainboard's Kconfig file. Stoney Ridge is available in FP4 and FT4 packages and each requires a unique binaryPI image. Default to the correct blob used by the northbridge by looking at the CPU's package. Also modify Gardenia to select the right package. See the Infrastructure Roadmap for FP4 (#53555) and FT4 (#55349) for additional details for the packages. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 7b8ed7b732b7cf5503862c5edc6537d672109aec) Change-Id: I7bb15bc4c85c5b4d3d5a6c926c4bc346a282ef27 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18989 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-18AMD binaryPI: Promote rules.h to default includeKyösti Mälkki
Also remove config.h, kconfig.h will pull that one in. Change-Id: I798b3ffcf86fca19ae4b0103bb901a69db734141 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17667 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-14vendorcode/amd: drop dead codePatrick Georgi
Change-Id: Ie67e1f7887e8df497d7dfd956badd9e06fd5d8a3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1254651 Reviewed-on: https://review.coreboot.org/17833 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-14vendorcode/amd: Fix non-terminating loopPatrick Georgi
Code is copied from agesa/common's amdlib.c. Things can probably be deduplicated. Change-Id: I9c8adab5db7e9fd41aecc522136dfa705c1e2ee6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1229662 Reviewed-on: https://review.coreboot.org/17834 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins)
2016-12-08buildsystem: Drop explicit (k)config.h includesKyösti Mälkki
We have kconfig.h auto-included and it pulls config.h too. Change-Id: I665a0a168b0d4d3b8f3a27203827b542769988da Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17655 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-07vendorcode/amd: Update Kconfig and makefiles for 00670F00Marc Jones
Add Stoney specific code subtree and fix Makefles and Kconfig files. Original-Author: Charles Marslett <charles@scarlettechnologies.com> Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 51a187a3d08a425ef0cc141a7ddc49a70ac931b1) Change-Id: I13c6b08c780e7bd2abd0fabbde1a89686132f65c Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17196 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07vendorcode/amd: Modify 0067F00 for binaryPIMarshall Dawson
Make changes to the vendorcode files that allow them to work with the binaryPI. This fixes various compile issues and establishes a common calling convention between coreboot and AGESA. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit f7ea2785d70bd6813b5b4d315b064802251d9557) Change-Id: Ie36228476a9dbd7b83f95828ca9c7252cecd8ec8 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17195 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07vendorcode/amd: Copy 00670F00 files from PI packageMarshall Dawson
Make exact copies of the AGESA files from the Stoney PI package replacing existing versions. Change the license text and fix up misc. whitespace. This will facilitate the review of binaryPI changes in the vendorcode directory. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 1097249585ab76fab59dcfbf8e7a419f34fcfcb6) Change-Id: I9951df58aeab2d533efc0a837ce35f343ff28d7c Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17194 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07vendorcode/amd: Copy 00660F01 directory to 00670F00Marc Jones
Prepare for new 00670FF00 support. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit ca53cac5c847c55e56ad6f5feb382c04f33ae77a) Change-Id: Ib48b1611bf70ec302c50f6e07bd2b3d9b09e0a24 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17193 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-02vendorcode/amd/pi/Kconfig: update AGESA_BINARY_PI_LOCATION to hexMartin Roth
The AGESA_BINARY_PI_LOCATION Kconfig symbol was declared as a string. Change it to a hex value. Change-Id: Ifd87b6c8dfcdf950aea9b15a6fea45bb72e8b4e9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16835 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-09vendorcode/amd: Remove dead codePatrick Georgi
Change-Id: I6b21822d60d379cb8cd21b69c714a437bb7977ce Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1254643 and others Reviewed-on: https://review.coreboot.org/16112 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-08vendorcode/amd/pi/Lib: Fix reporting fatal errorPatrick Georgi
Instead of writing the first word of 6 "post code structs" where only one exists (leading to 0xDEAD and 5 garbage words), write the correct set. Change-Id: Ifdfa53a970dda33dc9dc8c05788875077c001ecf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1361054, #1361055, #1361056 Reviewed-on: https://review.coreboot.org/16058 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-27Rename VB_SOURCE to VBOOT_SOURCE for increased clarityPaul Kocialkowski
This renames the VB_SOURCE variable to VBOOT_SOURCE in the build system, providing increased clarity about what it represents. Since the submodule itself is called "vboot", it makes sense to use that name in full instead of a very shortened (and confusing) version of it. Change-Id: Ib343b6642363665ec1205134832498a59b7c4a26 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15824 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-29src/: Chmod 644 all .c, .h, .asl, .inc, .cb, .hex, & Kconfig filesMartin Roth
Some trivial cleanup. Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13427 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-28Makefile: Make full use of src-to-obj macroNico Huber
There were several spots in the tree where the path to a per class object file was hardcoded. To make use of the src-to-obj macro for this, it had to be moved before the inclusion of subdirs. Which is fine, as it doesn't have dependencies beside $(obj). Tested by verifying that the resulting coreboot.rom files didn't change for all of Jenkins' abuild configurations. Change-Id: I2eb1beeb8ae55872edfd95f750d7d5a1cee474c4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13180 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06commonlib: Add function to hash contents of a CBFS region.Aaron Durbin
Provide a common routine to hash the contents of a cbfs region. The cbfs region is hashed in the following order: 1. potential cbfs header at offset 0 2. potential cbfs header retlative offset at cbfs size - 4 3. For each file the metadata of the file. 4. For each non-empty file the data of the file. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Utilized in chromeos cros_bundle_firmware as well as at runtime during vboot verification on glados. Change-Id: Ie1e5db5b8a80d9465e88d3f69f5367d887bdf73f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12786 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-11-12AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.1zbao
1. This is required the BLOB change Ie86bb0cf AMD Merlin Falcon: Update to CarrizoPI 1.1.0.1 (Binary PI 1.5) 2. This is tested on Bettong Alfa(DDR3) and Beta(DDR4). Both of the boards can boot to Windows 10. PCIe slots, USB and NIC work. Change-Id: I6cf3e333899f1eb2c00ca84c96deadeea0e23b07 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11752 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-06amd/pi/Makefile: Remove cp option '-u'zbao
"-u" is only for GNU cp. Cp of BSD and Solaris don't take this option. It is not necessary to compare the files before copying. Change-Id: I60cf57991275db0e075278f77a95ca5b8b941c7f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11601 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-30vendorcode/amd: 64bit fixesStefan Reinauer
Change-Id: I6a0752cf0c0e484e670acca97c4991b5578845fb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11081 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-22coreboot: introduce commonlibAaron Durbin
Instead of reaching into src/include and re-writing code allow for cleaner code sharing within coreboot and its utilities. The additional thing needed at this point is for the utilities to provide a printk() declaration within a <console/console.h> file. That way code which uses printk() can than be mapped properly to verbosity of utility parameters. Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11592 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-16AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.0WANG Siyuan
This is required the BLOB change Icb7a4f07 "AMD Merlin Falcon: Update to CarrizoPI 1.1.0.0 (Binary PI 1.4)" This is tested on Bettong Alfa(DDR3) and Beta(DDR4). Both of the boards can boot to Windows 8.1. PCIe slots, USB and NIC work. Change-Id: Ibe141c16f8f9eac2adc5d5f45a1f354fb2a7f33c Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/11148 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-09-16AMD Steppe Eagle: update vendorcode header files to MullinsPI 1.0.0.AWANG Siyuan
This is required the BLOB change I67817dc59 AMD Steppe Eagle: Update to MullinsPI 1.0.0.A (Binary PI 1.1). This is tested on Olive Hill Plus. The board can boot to Windows 7. PCIe slot, USB and NIC work. Change-Id: I605df26b61bdffabd74846206ad0b7bf677ebed1 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/11225 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-07vendorcode: Move AMD sources from blobs to vendorcodeMarc Jones
The AMD AGESA binaryPI sources were incorrectly committed to 3rdparty/blobs. Move them from blobs to vendorcode and fix Kconfig and Makefile.inc to match. Change-Id: I55a777553c1203464d7f7f4293b361fedcfa3283 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10982 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-05vendorcode: Fixup AGESA PI Kconfig variablesMarc Jones
The *_SELECTED Kconfig variables are not needed with the options contained within "if CPU_AMD_AGESA_BINARY_PI" introduced in e4c17ce8. It also removes the need to source and select the default prior to selecting the AGESA source or AGESA PI option. Change-Id: Iffa366f575f7f155bd6c7e7ece2a985f747c83be Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10981 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-30AMD binary PI: add vendorcode support for fan controlWANG Siyuan
Binary PI doesn't provide fan control lib. HwmLateService.c and ImcLib.c are ported from Kabini PI. I have tested on AMD Bettong. The two files work. Change-Id: Ia4d24650d2a5544674e9d44c502e8fd9da0b55d3 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10719 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-13vendorcode/amd: unify amdlib for binary piStefan Reinauer
Instead of having three copies of amdlib, the glue code for Agesa, let's share the code between all implementations (and come up with a versioned API if needed at some point in the future) Change-Id: I38edffd1bbb04785765d20ca30908a1101c0dda0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10507 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-13AMD Merlin Falcon: Add binary PI vendorcode filesWANG Siyuan
Add all of the PI source that will remain part of coreboot to build with a binary AGESA PI BLOB. This includes the gcc makefiles, some Kconfig, and the AGESA standard library functions. Change vendorcode Makefile and Kconfig so that they can compile AMD library files and use headers from outside the coreboot/src tree. Change-Id: Iad26689292eb123d735023dd29ef3d47396076ea Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10416 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-13amd/pi: Move AGESA cbfs access into the wrapperMarc Jones
The AGESA.c file in 3rdparty has cbfs access functions for locating the AGESA binaries. coreboot access functions need to be within coreboot where they can be updated with cbfs changes. Move the offending function to coreboot. Change-Id: Ibf6136d04dfbdb0198e90cc3ce719dc286c5610e Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10058 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-053rdparty: move to 3rdparty/blobsPatrick Georgi
There's now room for other repositories under 3rdparty. Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10109 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-053rdparty: Move to blobsPatrick Georgi
To move 3rdparty to 3rdparty/blobs (ie. below itself from git's broken perspective), we need to work around it - since some git implementations don't like the direct approach. Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-27southbridge/amd/pi: Rename Avalon to HudsonDave Frodin
To maintain consistancy with southbridge/amd/agesa/hudson rename pi/avalon to pi/hudson in advance of adding support for the base hudson southbridge. Change-Id: Icff8c4c06aae2d40cbd9e90903754735ac3510c3 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8251 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27AMD Bald Eagle: Add binary PI vendorcode filesBruce Griffith
Add all of the PI source that will remain part of coreboot to build with a binary AGESA PI BLOB. This includes the gcc makefiles, some Kconfig, and the AGESA standard library functions. Change vendorcode Makefile and Kconfig so that they can compile AMD library files and use headers from outside the coreboot/src tree. This fix changes the makefile so that the AGESA dispatcher is built using its own rules rather than generic library generation rules in coreboot/Makefile and coreboot/Makefile.inc. The AGESA source files are initially copied from whereever they live into coreboot/build/agesa. They are compiled from there. The binary PI directory now has a mandatory structure that places the AGESA BLOB into the same directory as the support headers. These will nominally be placed in the amd directory in SageBIOS or the 3rdparty directory in coreboot.org. Change-Id: I56788cd197159939b64c7d16c1d32418f8cc2197 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/5967 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-12vendorcode/amd/pi/00730F01/Lib/amdlib.c: Remove optimize attributeBruce Griffith
Remove '__attribute__((optimize("Os")))' as it is unlikely to be necessary as it is not used in other families that have the same code and only hides deeper issues. Change-Id: Ica890812ebc2fb659b9c3e46b40cf3f6534b3cf2 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/7689 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-20AMD: Isolate AGESA and PI build environments for southbridgeKyösti Mälkki
To backport features introduced with recent Chromebooks and/or Intel boards in general, heavy work on the AMD AGESA platform infrastructure is required. With the AGESA PI available in binary form only, community members have little means to verify, debug and develop for the said platforms. Thus it makes sense to fork the existing agesawrapper interfaces, to give AMD PI platforms a clean and independent sandbox. New directory layout reflects the separation already taken place under 3rdparty/ and vendorcode/. Change-Id: Ia730f0e45e7c1bdfc0c91e95eb6729a77773e2b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7388 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Tested-by: build bot (Jenkins)
2014-11-20AMD: Isolate AGESA and PI build environmentsKyösti Mälkki
To backport features introduced with recent Chromebooks and/or Intel boards in general, heavy work on the AMD AGESA platform infrastructure is required. With the AGESA PI available in binary form only, community members have little means to verify, debug and develop for the said platforms. Thus it makes sense to fork the existing agesawrapper interfaces, to give AMD PI platforms a clean and independent sandbox. New directory layout reflects the separation already taken place under 3rdparty/ and vendorcode/. Change-Id: Ib60861266f8a70666617dde811663f2d5891a9e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7149 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Tested-by: build bot (Jenkins)
2014-11-09src: Too many terminators ';;' at end of stmts, stop SkynetEdward O'Callaghan
Change-Id: I3e9b7e0e5558a6942067dcea04b83fe3bccbbaf9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-09AGESA stub 00730F01: Add config.h and kconfig.h to Makefile.incBruce Griffith
The static library builder for the stub that interfaces to the AGESA binary does not include config.h and kconfig.h, so any header file changes that depend on Kconfig variables fail. Force these two system headers to be included in the build of any AGESA stub files. Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Change-Id: I2e8d38fa5aa21cc31b995ee3abe68ab3c3c55a68 Reviewed-on: http://review.coreboot.org/6979 Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins)
2014-08-30AMD Steppe Eagle: Add binary PI vendorcode filesBruce Griffith
Add all of the PI source that will remain part of coreboot to build with a binary AGESA PI BLOB. This includes the gcc makefiles, some Kconfig, and the AGESA standard library functions. Change vendorcode Makefile and Kconfig so that they can compile AMD library files and use headers from outside the coreboot/src tree. The AGESA dispatcher is built using its own rules rather than generic library generation rules in coreboot/Makefile and coreboot/Makefile.inc. The AGESA source files are initially copied from whereever they live into coreboot/build/agesa. They are compiled from there. The binary PI directory has a mandatory structure that places the AGESA BLOB into the same directory as the support headers. These will nominally be placed in the 3rdparty directory in coreboot.org. The copy commands that were added to the the vendorcode Makefile.inc ensure that only one thread will operate on each source file by using a macro to generate the copy targets. After the change, each copy target will operate on exactly one source file. Due to API issues, coreboot has no way to control the IMC to set up fan control. Set a Kconfig flag that removes the ability to install an IMC BLOB into CBFS. Change-Id: I050b72a19086aaeba6cb65ce165297b10e3cfc45 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6595 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
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