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The term MTRR has been misspelled in a few places.
Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change the cache-as-ram teardown to use invd instead of wbinvd.
Save the return and recover the call's return address in
chipset_teardown_car.
CAR teardown had been modified to use wbinvd to send CAR contents
to DRAM backing prior to teardown. This allowed CAR variables,
stack, and local variables to be preserved while running the
AMD_DISABLE_STACK macro.
Using the wbinvd instruction has the side effect of sending all
dirty cache contents to DRAM and not only our CAR data. This
would likely cause corruption, e.g. during S3 resume.
Stoney Ridge now uses a postcar stage and this is no longer a
requirement.
BUG=b:64768556
Change-Id: I8e6bcb3947f508b1db1a42fd0714bba70074837a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20967
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove register preservations that are not required and
fix comments about register usage accordingly.
Change-Id: Ibc9ed982ac55e947c100739250db122033348a82
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20576
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clean up commentary on AMD_DISABLE_STACK to be clear that
it does a wbinvd to preserve coreboot CBMEM and
value of car_migrated.
Change-Id: I1265ed3d1bdf4b22f1a56f68bc53e18cfadc44b2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Prepare for new 00670FF00 support.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit ca53cac5c847c55e56ad6f5feb382c04f33ae77a)
Change-Id: Ib48b1611bf70ec302c50f6e07bd2b3d9b09e0a24
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17193
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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