| Age | Commit message (Collapse) | Author |
|---|
|
ITE super-i/o chips need a fourth byte and have a special register
to exit config mode.
Change-Id: Ic40873649d567b87d3a937f2bf068649e67715de
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17286
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Change-Id: I8cbfe49516e685c1b3e150b23f9fcac513f1f3dc
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17285
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
The purpose of this change is to enable serial output in
bootblock stage
Change-Id: I8e075f1e70d1a6598dfdc34931218f5af9637178
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/17359
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The devicetree parameter already existed without being
used in the code.
Change-Id: I99dd8bc7a9b2f3509a115a130062d462a62e33fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17614
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: I25019c6323b6e9de2e0ce19325266bf3e8f2e309
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17581
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This is a stopgap for when you use SUPERIO_SMSC_SMSCSUPERIO and the
interrupt is unmapped at reset, but for whatever reason the chip is
inaccessible in smscsuperio/superio.c::enable_dev() and thus the
devicetree.cb IRQ information is not applied in ramstage and then
serial console output fails to work for more than the UART FIFO depth
in the OS.
Change-Id: I00998088975569516f7caeb7f4098b48fe437889
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/10807
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: I597ba3a03bd42c64d03137b10a3758d86b129029
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17452
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The environment-controller entity is shared by many ITE super-i/o
chips. There are some differences between the chips, though. To cover
that, the super-i/o chip should select Kconfig options of this driver
accordingly.
The current implementation isn't exhaustive: It covers only those
parts that are connected on boards I could test, plus those that are
currently used by the IT8772F. The latter could be ported to use this
driver if somebody minds to test it.
Change-Id: I7a40f677f667d103ce1d09a3e468915729067803
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17284
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I5f88f34d1c040ac6ed413cfaf8ceb45a358c117c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17048
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: Ie2062672233141b6f34625e59cbb50238be0b5fa
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16726
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Revert commit 53552cc0 (Drop SuperIO nuvoton/nct6776),
removing the code as no other mainboard uses it.
The board Intel Saddle Brook uses this device, so add the
code back with minor adaptations.
Change-Id: I546879285ad8336e81798d0fbdf94f72e1fa61a2
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/16519
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Ibeab5e7fe0a9005e96934b3b43cfb247ef2e2340
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16615
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I8597d205ca84bee0171c3d45549a28b58a050529
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16433
Tested-by: build bot (Jenkins)
Reviewed-by: Antonello Dettori <dev@dettori.io>
|
|
All but ga-g41m-es2l/cmos.default had multiple final newlines.
ga-g41m-es2l/cmos.default had no final newline.
Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16361
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Antonello Dettori <dev@dettori.io>
|
|
This moves the Kconfig from the Super I/O manufacturer folder
to the chip folder instead.
This makes new chip commits self-contained unit as
edits to the central Kconfig file are no longer required.
Change-Id: I7aee07919f2ae9204850c669e0ed3cb17d4de8cd
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/15973
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
|
|
Pins for UART 3/4 are by default GPIO pins.
This patch sets the pins in UART mode.
Since UART 1/3 and 2/4 share the same interrupt line,
the patch needs to enable also shared interrupts.
Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P
Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html
Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15564
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
This adds support for Nuvoton NCT6791D Super I/O chips.
Makes use of the common Nuvoton early_serial.c.
Based on the Datasheet supplied by Nuvoton.
Datasheet Version: January 8th, 2016 Revision 1.11
Change-Id: I027d33b85f0dc6ee50deebdccaecc74487eecb40
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/15967
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Change-Id: Ib98c69de781d2b651ec168d03250cacc918c5c1f
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/14965
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Certain mainboards require SuperIO pinmux configuration before
peripherals will become operational. Allow each mainboard to
configure the pinmux(es) of Winbond chips if needed.
Change-Id: Ice19f8d8514b66b15920a5b893700d636ed75cec
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/14960
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Certain mainboards, e.g. the ASUS KGPE-D16/KCMA-D8, require
board-specific configuration changes to the SuperIO. Expose
the functions needed to enter and exit configuration mode
on Winbond devices.
Change-Id: Ic86651872ecafcfe1398201be2b0768bbe460975
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14891
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The way this was implemented before was causing ACPI failures. There
was also a basic misunderstanding of what the AddressMax field was used
for. In this case, because it's a fixed address, it should be the same
as the AddressMin field.
Getting rid of the addition in the field solves the ACPI output problem.
Change-Id: Idec2bf0ed27ae694e98f141087cdf22401937178
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14343
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
|
|
This resolves error messages of the form:
ERROR: device PNP: 002e.6 index 98 has no mask.
Change-Id: I6a368b902d051c8da6f74cbde54f5d12a3e52c2f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14272
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
The official spelling of Nuvoton is not all uppercase. Only the first
letter is uppercase. See the footer of the Nuvoton Web site.
Change-Id: I6ccd4194d7be0c89f8b332fcca5feb2420a4de1e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/5928
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Remove dependency on early_serial.c and instead use the
Super I/O's header to access the functions needed.
Also re-organize some of the superio code in order
to succesfully compile the rom.
Change-Id: I85a6f1352ae3b91c3c98e4d3fa0b90b87e02babc
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/13925
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Remove dependency on early_serial.c and instead use the
Super I/O's header to access the functions needed.
Change-Id: I9edf7fc2501aa832106dda9213e702dbcc1200b4
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/13887
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
|
On certain Super I/O devices, when a PS/2 mouse is not present on the
auxiliary channel both channels will cease to function if the
auxiliary channel is probed while the primary channel is active.
Therefore, knowledge of mouse presence must be gathered by coreboot
during early boot, and used to enable or disable the auxiliary PS/2
port before control is passed to the operating system.
This is added in commit 448e3863 (drivers/pc80: Add PS/2 mouse
presence detect).
Update the Nuvoton NCT5572D driver to flag the auxiliary channel as
disabled if no device was detected. The code is copied from the Winbond
W83667HG-A driver.
Note, the ACPI changes are not part of this commit.
TEST=Currently, on the ASRock E350M1, PS/2 does not work. With this
change, a PS/2 keyboard works fine in SeaBIOS, GRUB in MBR, and Debian
GNU/Linux Sid/unstable with Linux 3.19.
```
[ 1.185195] i8042: PNP: No PS/2 controller found. Probing ports directly.
[ 1.189110] serio: i8042 KBD port at 0x60,0x64 irq 1
[ 1.189133] serio: i8042 AUX port at 0x60,0x64 irq 12
[ 1.189970] mousedev: PS/2 mouse device common for all mice
```
Change-Id: I7f9be348d295e70437bef089d4c2173169f38459
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/13618
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
On certain Winbond SuperIO devices, when a PS/2 mouse is not
present on the auxiliary channel both channels will cease to
function if the auxiliary channel is probed while the primary
channel is active. Therefore, knowledge of mouse presence
must be gathered by coreboot during early boot, and used to
enable or disable the auxiliary PS/2 port before control is
passed to the operating system.
Add auxiliary channel PS/2 device presence detect, and update
the Winbond W83667HG-A driver to flag the auxiliary channel as
disabled if no device was detected.
Change-Id: I76274493dacc9016ac6d0dff8548d1dc931c6266
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13165
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The KGPE-D16 and KCMA-D8 use a Winbond W83667HG-A SuperIO. While
the Nuvoton NCT5572D is effectively the same core, and a close
enough match to get things working initially, the W83667HG-A
has a different LDN mapping and several extra features that
require a separate support driver.
Clone the Nuvoton NCT5572D and modify according to the W83667HG-A
datasheet, version 1.4.
Change-Id: I707ba2e40a22d41cd813003d84a82cb20304f55b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13156
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
This just updates existing guard name comments on the header files
to match the actual #define name.
As a side effect, if there was no newline at the end of these files,
one was added.
Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12900
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This continues what was done in commit a73b93157f2
(tree: drop last paragraph of GPL copyright header)
Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12914
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
- occured -> occurred
- accomodate -> accommodate
- existant -> existent
- asssertion -> assertion
- manangement -> management
- cotroller -> controller
Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12850
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Original-Signed-off-by: Ted Kuo <tedkuo@ami.com.tw>
Change-Id: I70d7b572e9ae030136a39fb6fa933f486d559aef
Original-Reviewed-on: https://chromium-review.googlesource.com/262832
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Commit-Queue: Ted Kuo <tedkuo@ami.com.tw>
Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12799
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Set up External Temperature to read via thermal diode/resistor
into TMPINx register by setting thermal_mode switch.
Original-Signed-off-by: Ted Kuo <tedkuo@ami.com.tw>
Change-Id: I0e8621b92faa5c6246e009d2f852c8d4db484034
Original-Reviewed-on: https://chromium-review.googlesource.com/260545
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw>
Original-(cherry picked from commit 973e2d393f2595b756f8aa20f6fbe3b6e045621a)
Original-Reviewed-on: https://chromium-review.googlesource.com/262340
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12798
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Change-Id: Id6d50d4d6af31e43f851645f09383121755291f6
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12815
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
According to the PNP ISA v1.0a spec, config registers in the range of
0xf0 up to 0xfe are vendor defined and may be used for any purpose.
Config register 0xff is reserved and is defined as such.
Currently, only vendor specific registers 0xf0, 0xf1, 0xf4, and 0xfa
are able to be set using the PNP_MSCx bit flag masks.
This patch adds support for all 15 vendor specific config registers,
and updates the existing superio pnp_info to use them where appropriate.
Change-Id: Id43b85f74e3192b17dbd7e54c4c6136a2e59ad55
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12808
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
- Remove it8772f c includes
- Add a new LED API, it8772f_gpio_led
- Stumpy: using it8772f_gpio_led
BUG=chrome-os-partner:28232
BRANCH=Guado
TEST=emerge-guado coreboot chromeos-bootimage
Change-Id: I08de52515d3c1e7e85d1761c09a0cebffda7dda3
Signed-off-by: David Wu <David_Wu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/241813
Tested-by: David Wu <david_wu@quantatw.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: David Wu <david_wu@quantatw.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12797
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
The SIO device needs to provide an _ADR object with the IO
address as well as the address in the OperationRegion.
ACPI provides two different Resource Descriptor Macros to describe the
I/O areas required for a device. The FixedIO macro is only valid for
10-bit IO addresses. Use the IO macro instead.
Thank you to recent IASL that allows for addition in the ASL file. :)
Fixes these warnings:
dsdt.aml 2276: Device (SIO) {
Warning 3141 - ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml 2390: FixedIO (0xa00, 0x34)
Warning 3060 - ^ Maximum 10-bit ISA address (0x3FF)
dsdt.aml 2394: FixedIO (0xa00, 0x34)
Warning 3060 - ^ Maximum 10-bit ISA address (0x3FF)
Lumpy now compiles its ASL tables with no warnings. Re-enable
Warnings as errors.
Change-Id: Id26e234eadaa3b966e8f769cb9f9fb7ea64fc9e3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12520
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This reverts commit 42444f6f53d47604d9a44c9e109b5717efaed74f.
Change-Id: Ifaaaad715d94c3c9ff365745aa2e6ee546924f4f
Reviewed-on: http://review.coreboot.org/12328
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
All boards using this SuperIO have been removed from the tree already.
Change-Id: I3c43a431d92d76b6ed3ec72b203d3e80925cadea
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12247
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
The Intel i8900 Super I/O is similar to the previously
supported i3100.
Change-Id: I9a5b651cab35991c3c3e09fc4668d35ca2d221ba
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12169
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: York Yang <york.yang@intel.com>
|
|
The Winbond WPCD376I is a desktop Super I/O often selected on
Intel mainboards. The support is similar to other Winbond and NSC SIOs.
Based on output from superiotool -d.
Change-Id: Ib4786b410b1d83606e8d79a9f686c14a5d25cadf
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12165
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
All boards using this SuperIO have been removed from the tree already.
Change-Id: I52847bc2fc16b27ac0de0bc7c847221b1e5cb744
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12245
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
While the actual pins behind these devices are not exposed on the chip,
the enable registers are implemented in hardware. Allow to turn these LDNs
off, like the vendor bios for asrock/e350m1 does.
Change-Id: I4d6d5a8de12b09095138cacbad62b2dfbbe54028
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12213
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
All boards using this SuperIO have been removed from the tree already.
Change-Id: I57eacf2a88077d0d0bffdcf44b3c2ecbd301e625
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12242
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
All boards using this SuperIO have been removed from the tree already.
Change-Id: Ifca91ae44ab222371808ff1e0027a7cbd4646b0a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12243
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
All boards using this SuperIO have been removed from the tree already.
Change-Id: Ic5604c75de249b945dca58aa904edec86558d3ec
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12241
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
All boards using this SuperIO have been removed already.
Change-Id: I667a8d15a2d16671115f62de656b1c5c6a8259b9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12240
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
All boards using this SuperIO have been removed from the tree.
Change-Id: I1d13ec7c5f27e82523612af7f07fca3176953600
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12239
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Change-Id: Ia0313b9ecd64c9e6f99a140772ebb35abe0175fd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11950
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: If2ba9ca48c809fe4f7dc0595a3cb3df168d630fd
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10893
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: I3218bfaaa64bcad54fe97c6f887025356ccc9356
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10892
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: I2ddb5a8b183b21cbd3c3b22c537b815e86bd4738
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10592
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Kconfig sometimes fails to parse the last line of a file if there's
no newline at the end. Add one to be safe.
Change-Id: Ia9973a89b12596e1f2a2741ad2e255e886495331
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10614
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This patch adds support for the Fintek F81866AD-I SuperIO,
which is very similar to the fintek/f81865f.
This code adds some fan control support, inspired by fintek/f71869ad.
Furthermore its possible to change the temp sensor type (thermistor or diode).
Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P
Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html
Change-Id: Id2fc1119b37142f8101f71908e394ee69c45041d
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: http://review.coreboot.org/10287
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Use of scan_static_bus() and tree traversals is somewhat convoluted.
Start cleaning this up by assigning each path type with separate
static scan_bus() function.
For ME, SMBus and LPC paths a bus cannot expose bridges, as those would
add to the number of encountered PCI buses.
Change-Id: I8bb11450516faad4fa33b8f69bce5b9978ec75e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8534
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
|
|
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
|
|
Add support for Nuvoton NCT6779D, using NCT6776 as a baseline
Change-Id: I020a21267f7e30bdea4bb5f83d67bd94082fdf05
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10232
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Change-Id: Ib4ee3633d210a05e06ed95fc13830cc692095501
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/10235
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Replace the multiple indexed I/O read and write
functions with common functions.
Change-Id: Idfe7a8784c28d51b3fbcb2f4e26beaa0b91741a8
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/10145
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
Routing is decided based on enabled logical/virtual devices.
For a valid devicetree, one should have only one of SP3 and GPIO0,
and only one of SP4 and GPIO1, enabled at a time in configuration.
Change-Id: I02017786aba9dd22d12403aaa71d7641f5bbf997
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10177
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
|
|
That function was getting too long.
Change-Id: Ic50f210391c2467b65215aa556269b0ba601c2ec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10176
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
|
|
With kconfig understanding wildcards, we don't need
Kconfig files that just include other Kconfig files
anymore.
Change-Id: I7584e675f78fcb4ff1fdb0731e340533c5bc040d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9298
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
It causes fan top speed due to this bug + our board-specific workaround,
and causes invalid temperature sensor readings.
Therefore, re-configure the register "External Temperature Sensor Host
Control Register" to terminate processes when this issue happens.
BUG=chromium:402204
TEST=ran suspend_stress_test 500 times
Change-Id: I439d5de798fbe999e4eec5497e6969b7b453121b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b82f2922c7fce3ca6b2797a8d9775e9db2817fe9
Original-Change-Id: I6e71b6a46a31b00e541c304f1ed58c1678c1d42e
Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219445
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/8820
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The actual key values were not added in commit 17ace8255.
TEST: amd/lamar shows the correct result.
Change-Id: I8f20e3d0ce83dd87b6c233ee98c3e77a6b7c1b03
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8375
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: Marc Jones <marc.jones@se-eng.com>
|
|
The amd/lamar mainboard is the first mainboard to use the f81216h.
These changes are needed to fix up commit 27a63d77 so the
Super I/O builds and functions correctly.
- Wrong #include name
- Removed global variable in romstage
- Missing "case" in switch()
Change-Id: I1b2058a915b776664fba14e4341e8a410b50330f
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8255
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the superio code to use printk() on all non-ROMCC
boards.
Change-Id: I23fc307f1346cdb7adaaeccfafe17d9205e909ac
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8113
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
|
|
This code is unused, and the same functionality is in superiotool
already.
Change-Id: I7bf667e2e2bfc8fdedcdbe09bf420abf47b1ee97
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8112
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Provide proper Makefile and Kconfig components so
that this superio is built as object code. Select
superio component in mainboard Kconfig's to bring
in the link-time symbols and thereby removing the
need for .c inclusion.
N.B. The LPC47N207 Super I/O does not physically exist
on these boards. The Super I/O is found on external LPC
debug card hardware and so should really be made selectable.
However, this is beyond the scope of this specific fix, that
rids us of .c inclusions in romstage.c
Change-Id: I451c3a81c4b5beca1ed65e27467a7393d2521dae
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8084
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Remove dead debug code, we have superiotool for this reason.
Restructure file to be consistent with other superio's thereby
avoiding forward declarations of functions.
Change-Id: I44272b4e30a2bc8c3a719df17b837432cd38429c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8083
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Remove dead debug code, we have superiotool for this reason.
Restructure file to be consistent with other superio's thereby
avoiding forward declarations of functions.
Change-Id: Ief60d3f54c508cbb7795b284b59710d2c0e3018b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8082
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: Id3d5f2a120c0a933c031102f206829305da20f0c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8081
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: I4a3639c05231eacd016ec3873330f9844befd448
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8080
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: I344f2a8d2ae5f6f3fa04d79773ee1c59de69e425
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8079
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
|
|
Change-Id: I2efb7ab4b69bcd127b2faf54277dc229c9dcf3ea
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8078
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
|
|
Change-Id: Id156ca3c9a14c5bcc4d6cdb8434ca8efdac3139a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8077
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: Ia45bc7a880d0dab57c56a0452858cd26626f09df
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8076
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: I83db9b189e672b0e1f25bc42b73639c375bea3e5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8054
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: Id6d9efc93fdaff63dcaab50712ac9be35ccb42a7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8053
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
There is no Cache As Ram for these boards, let's get rid of them.
Also drop unused dependencies
Change-Id: I94782da521c32ade7891ada29d3013cbab32a48b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7836
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Drop two SuperIOs that were only used by GX1 systems, and are not used anymore.
* winbond/w83977f
* nsc/pc87351
Change-Id: I8a8eacb0f862b5d08ccfd87f8db503b0ab3c5700
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7118
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
No need to mark Makefiles, C files or devicetrees
executable.
Change-Id: Ide3a0efc5b14f2cbd7e2a65c541b52491575bb78
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7618
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
We already have these implemented under superio/common, use
those instead of this copy-paste syndrom.
Change-Id: I7c7737e0b3c284d8b14b36c70681ab2269bb1d4b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7310
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: I20a34b569f109dd12af29e9e0cee8f7f6b8ebb80
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7309
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
|
|
Super I/O manufactures have found new and innovative ways to enter
and exit out of LDN config in PNP config space.
Change-Id: Id3f5882664f1b2b18b49f32373430cf4b037ad22
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7308
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
|
|
Add support for both NCT6776D and NCT6776F devices.
Change-Id: If6686ea0a1cd6be537e286699b4ee8f88ba8ad7c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/5450
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Change-Id: I3b720cf879bf5326be885d2d3a3f9cfba0a27c7e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/6229
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
|
|
Change-Id: Id88bb4367d6045f6fbf185f0562ac72c04ee5f84
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/7146
Tested-by: build bot (Jenkins)
|
|
Hiding pointer types behind 'typedef's is usually not a great
idea at the best of times. Worse the typedef becomes an integer
at different stages in Coreboot. Let us refrain from doing this
at all.
Change-Id: Ia2ca8c98bb489daaa58f379433875864f6efabc8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7136
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
The romstage component of Super I/O support is in fact written around
passing a lower and upper half packed integer. We currently have two
typedef's for this, 'device_t' and 'pnp_devfn_t'. We wish to make use of
'pnp_devfn_t' over 'device_t' as 'device_t' changes it's typedef in the
ramstage context and so is really a conflicting definition. This helps
solve problems down the road to having the 'real' 'device_t' definition
usable in romstage later.
This follows on from the rational given in:
c2956e7 device/pci_early.c: Mixes up variants of a typedefs to 'u32'
Change-Id: Ia9f238ebb944f9fe7b274621ee0c09a6de288a76
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6231
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
|
|
Change-Id: Ia1bbf2f885acf601b8a8360a7cd72819f70ef6a6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7137
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
|
|
Change-Id: I602f970e0ee2fd634a74fd4c25358c2e78ca58f9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/179536
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 02b0583e632f1ba53557f8cfe4293ad4ed29ff4d)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6910
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Change-Id: I45885905f0adaa8f0ad9137d7034e6f7a0dc43de
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175356
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 7fe642543a8de249e13c3d63c3302a20910c247d)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6859
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Clean up both ram and rom stage support and fix board to match.
Change-Id: I55e3e7338c0551f0fb663eb9707f16ecdc1aca35
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6509
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
|
|
Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE
as argument instead of hard coding and playing funny business with the
pre-processor. Fix board to match.
Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6463
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
|
|
Remove spurious includes, unused variables and some wasted new lines.
Re-organise things to be consistent with other superio's.
Change-Id: I959bab2f7a83a1b9160d7f010a0de9638b30cf07
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6465
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
|
|
Change-Id: I5d0a945de45f8f4a77193135e63f480af14a0136
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/6279
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Provide proper header and function type-signatures for Super I/O
romstage component.
Fix mainboard's bogous romstage component to match.
Change-Id: Icd02199690d0c428b2daadf702d50714dc367692
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5924
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Change-Id: Id3f85929024208b150c378d7636607a0c9b8617c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6302
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Remove #include early_serial.c and rename to early_init.c as no actual
UART configuration is done here. Note that this SIO component still
hard codes its base address to 0x2e.
Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6271
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
