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2022-12-14sio/winbond/w83627hf/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I6858ddaa8b70194ffdd3b4edcb0ee57aec262b48 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14sio/winbond/w83667hg-a/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I3809880312af4736407e361da53f0424280e43d4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14superio/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: Ibbecba97dd1628889539c2962dd31964c252c8bb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12{drivers,superio}/acpi: Replace ShiftRight(a,b) with ASL 2.0 syntaxFelix Singer
Replace `ShiftRight (a, b)` with `a >> b`. Change-Id: I0751d00186e8dff38e02e7bf7d8ebf5a17514a58 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12{soc,superio}/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Subtract (a, b, c)` with `c = a - b`. Change-Id: If6455ab2c91619f884abae227f1ac2e2c2af6ba9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-05superio/ite/it8772f/chip.h: Use 'bool' when appropriateElyes Haouas
Change-Id: I20c3298a920396718f0dc036e57faf8e46b82b2c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70253 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05superio/aspeed/ast2400/chip.h: Include <stdbool.h>Elyes Haouas
Change-Id: Ib4a0d77e7bb4cb52e91a5965cae0a6c7ddc40090 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70254 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-21src/superio: Remove unnecessary space after castsElyes Haouas
Change-Id: Iab76316f345fb0cf2ca2a3eaf40f64a1f1b7fc13 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69814 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17{ec/superio}/acpi: Remove _PRS if no _SRS is implementedArthur Heymans
_PRS only makes sense if _SRS is implemented. Change-Id: I030bd716215b5ac5738e00ebf6ed991d9d6c5ca0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69513 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-17superio/acpi/pnp_generic.asl: Add _PRS for each deviceArthur Heymans
Simply return the current resource settings in the _PRS method. This means that coreboot has to correctly set up the resources on the device. This won't result in any regression as without _PRS the ACPI OS would not know what resources settings are valid, so it would never use _SRS. Change-Id: I2726714cbe076fc7c772c06883d8551400ff2baa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64218 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-09Revert "mb/aopen/dxplplusu: Remove board"Kyösti Mälkki
This reverts commit eb76a455cd39ec59b7f2ba28baeec9538befd59e and applies minor fixes to make it build again. PARALLEL_MP was working prior to board removal and no relevant SMI handlers were implemented. So NO_SMM choice is now selected. Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-09superio/nuvoton/nct6687d: Fix unexpected expressionArthur Heymans
Expression after a case statement are not allowed. This fixes building with clang. Change-Id: Ie369454f10b515aa5601a5e78330e12f4b7a5e4c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-07mb/aopen/dxplplusu: Remove boardArthur Heymans
This board use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: Idf37ade31ddb55697df1a65062c092a0a485e175 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69114 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-07superio/ite/common/early_serial.c: ite_kill_watchdog: set timeout to 0Michał Kopeć
Set the watchdog timeout to 0 in ite_kill_watchdog, as in some ITE models it is set to non-zero by default, activating the watchdog despite us setting the control register to 0. Based on: - "ITE IT8786E-I Preliminary Specification V0.4.1 (For D Version)" - Linux it87_wdt driver Change-Id: I1e78e2acc96e9dd0f283c5c674d3277d26cdee26 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-08superio/nuvoton/nct6687d: Add ramstage driver and ACPIMichał Żygowski
TEST=Boot MSI PRO Z690-A WIFI DDR4 with SP1, KBC and EC exposed to OS via ACPI. Configure SP1, ACPI, KBC and EC devices via devicetree. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia489a39956c1448c7f11845ecc9e1df83ccb25ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/63927 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09superio/winbond/w83667hg-a: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: I033f73e6552746c6899e46ee4d619ab47cb3d55b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09sio/winbond/w83627hf/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: I24cf4fd70e887c14006975f494be63c34f8a75e6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09sio/winbond/w83627hf/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: I9344e34058a1dd8b951d273e53e3c229a0ec07b4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09superio/winbond/w83627hf/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: I3833a3a341bd64191cc0b811ca80e96a359307a1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09superio/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: I407d061ac7664d4910b8759fd1a72eab133b6e22 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09superio/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: Ia09c54465af47f5779917ed71bb3ea148864dfd1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-05-16superio/nuvoton/nct6687d: Add early support for NCT6687DMichał Żygowski
Based on the public datasheet of NCT6686 which should be similar to NCT6687D. TEST=Enable serial for debugging on MSI PRO Z690-A WIFI DDR4 and see coreboot console on the debug port Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I0e8744b5958af196de3de63de31852029d81436e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-11superio/kbc1100: Fix set but unused variablesArthur Heymans
This fixes building with clang. Change-Id: I865038ffab9cd7be8aa6a42e629f108b55c08f59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2022-04-20superio/smsc/mec1308: Drop `_PRS` from static devicesAngel Pons
The `_PRS` ACPI object is not needed for static (non-configurable) devices. For devices where `_CRS` always provides the same set of resource settings, drop the `_PRS` object. Note that every dropped `_PRS` object only provides one set of resource settings, which is identical to the resource settings provided by the `_CRS` object. In addition, drop `IGNORE_IASL_MISSING_DEPENDENCY` from the two mainboards using the MEC1308 code, `samsung/{lumpy, stumpy}`. Change-Id: I5d5cdc28c2cfaa5dfcffd656060b931208977386 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20superio/smsc/sch5545: Drop `_PRS` from static devicesAngel Pons
The `_PRS` ACPI object is not needed for static (non-configurable) devices. For devices where `_CRS` always provides the same set of resource settings, drop the `_PRS` object. Note that every dropped `_PRS` object only provides one set of resource settings, which is identical to the resource settings provided by the `_CRS` object. In addition, drop `IGNORE_IASL_MISSING_DEPENDENCY` from the only mainboard using the SCH5545 code, `dell/snb_ivb_workstations`. Change-Id: Ic462bd3dfa287744d4f733561de81c09c1c397e6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-16Use the fallthrough statement in switch loopsArthur Heymans
Clang does not seem to work with 'fall through' in comments. Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-07treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner
Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-01-31superio/smsc/lpc47n207/early_serial.c: Fix indent for 'if' statementElyes HAOUAS
Change-Id: I0342e25747458239c1ad8c0f70f91f700ae8325d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10superio/smsc/sch5545/superio.c: Include `stdint.h` and `bsd/helpers.h`Elyes HAOUAS
Change-Id: I1b7778b039f57bee5bed4e6e0de562ca052eca39 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/superio/smsc: Remove unused <stdlib.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l 'memalign(\|malloc(\|calloc(\|free(' -- src/) Change-Id: Icb747bcb702a81750a927272432666ffe603ca55 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/superio: Remove unused <acpi/acpi.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <acpi/acpi.h>' -- src/) <(git grep -l 'SLP_EN\|SLP_TYP_SHIFT\|SLP_TYP\|SLP_TYP_S\|ACPI_TABLE_CREATOR\|OEM_ID\|ACPI_DSDT_REV_\|acpi_device_sleep_states\|ACPI_DEVICE_SLEEP\|RSDP_SIG\|ASLC\|ACPI_NAME_BUFFER_SIZE\|COREBOOT_ACPI_ID\|acpi_tables\|acpi_rsdp\|acpi_gen_regaddr\|ACPI_ADDRESS_SPACE\|ACPI_FFIXEDHW_\|ACPI_ACCESS_SIZE_\|ACPI_REG_MSR\|ACPI_REG_UNSUPPORTED\|ACPI_HID_\|acpi_table_header\|MAX_ACPI_TABLES\|acpi_rsdt\|acpi_xsdt\|acpi_hpet\|acpi_mcfg\|acpi_tcpa\|acpi_tpm2\|acpi_mcfg_mmconfig\|acpi_hmat\|acpi_hmat_mpda\|acpi_hmat_sllbi\|acpi_hmat_msci\|acpi_srat\|ACPI_SRAT_STRUCTURE_\|acpi_srat_lapic\|acpi_srat_mem\|acpi_srat_gia\|CPI_SRAT_GIA_DEV_HANDLE_\|acpi_slit\|acpi_madt\|acpi_lpit\|acpi_lpi_flags\|acpi_lpi_desc_type\|ACPI_LPI_DESC_TYPE_\|acpi_lpi_desc_hdr\|ACPI_LPIT_CTR_FREQ_TSC\|acpi_lpi_desc_ncst\|acpi_vfct_image_hdr\|acpi_vfct\|acpi_ivrs_info\|acpi_ivrs_ivhd\|acpi_ivrs\|acpi_crat_header\|ivhd11_iommu_attr\|acpi_ivrs_ivhd_11\|dev_scope_type\|SCOPE_PCI_\|SCOPE_IOAPIC\|SCOPE_MSI_HPET\|SCOPE_ACPI_NAMESPACE_DEVICE\|dev_scope\|dmar_type\|DMAR_\|DRHD_INCLUDE_PCI_ALL\|ATC_REQUIRED\|DMA_CTRL_PLATFORM_OPT_IN_FLAG\|dmar_entry\|dmar_rmrr_entry\|dmar_atsr_entry\|dmar_rhsa_entry\|dmar_andd_entry\|dmar_satc_entry\|acpi_dmar\|acpi_apic_types\|LOCAL_APIC,\|IO_APIC\|IRQ_SOURCE_OVERRIDE\|NMI_TYPE\|LOCAL_APIC_NMI\|LAPIC_ADDRESS_\|IO_SAPIC\|LOCAL_SAPIC\|PLATFORM_IRQ_SOURCES\|LOCAL_X2APIC\|GICC\|GICD\|GIC_MSI_FRAME\|GICR\|GIC_ITS\|acpi_madt_lapic\|acpi_madt_lapic_nmi\|ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS\|acpi_madt_ioapic\|acpi_madt_irqoverride\|acpi_madt_lx2apic\|acpi_madt_lx2apic_nmi\|ACPI_DBG2_PORT_\|acpi_dbg2_header\|acpi_dbg2_device\|acpi_fadt\|ACPI_FADT_\|PM_UNSPECIFIED\|PM_DESKTOP\|PM_MOBILE\|PM_WORKSTATION\|PM_ENTERPRISE_SERVER\|PM_SOHO_SERVER\|PM_APPLIANCE_PC\|PM_PERFORMANCE_SERVER\|PM_TABLET\|acpi_facs\|ACPI_FACS_\|acpi_ecdt\|acpi_hest\|acpi_hest_esd\|acpi_hest_hen\|acpi_bert\|acpi_hest_generic_data\|acpi_hest_generic_data_v300\|HEST_GENERIC_ENTRY_V300\|ACPI_GENERROR_\|acpi_generic_error_status\|GENERIC_ERR_STS_\|acpi_cstate\|acpi_sw_pstate\|acpi_xpss_sw_pstate\|acpi_tstate\|acpi_lpi_state_flags\|ACPI_LPI_STATE_\|acpi_lpi_state\|acpi_upc_type\|UPC_TYPE_\|acpi_ipmi_interface_type\|IPMI_INTERFACE_\|ACPI_IPMI_\|acpi_spmi\|ACPI_EINJ_\|ACTION_COUNT\|BEGIN_INJECT_OP\|GET_TRIGGER_ACTION_TABLE\|SET_ERROR_TYPE\|GET_ERROR_TYPE\|END_INJECT_OP\|EXECUTE_INJECT_OP\|CHECK_BUSY_STATUS\|GET_CMD_STATUS\|SET_ERROR_TYPE_WITH_ADDRESS\|TRIGGER_ERROR\|READ_REGISTER\|READ_REGISTER_VALUE\|WRITE_REGISTER\|WRITE_REGISTER_VALUE\|NO_OP\|acpi_gen_regaddr1\|acpi_einj_action_table\|acpi_injection_header\|acpi_einj_trigger_table\|set_error_type\|EINJ_PARAM_NUM\|acpi_einj_smi\|EINJ_DEF_TRIGGER_PORT\|FLAG_PRESERVE\|FLAG_IGNORE\|EINJ_REG_MEMORY\|EINJ_REG_IO\|acpi_einj\|acpi_create_einj\|fw_cfg_acpi_tables\|preload_acpi_dsdt\|write_acpi_tables\|acpi_fill_madt\|acpi_fill_ivrs_ioapic\|acpi_create_ssdt_generator\|acpi_write_bert\|acpi_create_fadt\|acpi_fill_fadt\|arch_fill_fadt\|soc_fill_fadt\|mainboard_fill_fadt\|acpi_fill_gnvs\|acpi_fill_cnvs\|update_ssdt\|update_ssdtx\|acpi_fill_lpit\|acpi_checksum\|acpi_add_table\|acpi_create_madt_lapic\|acpi_create_madt_ioapic\|acpi_create_madt_irqoverride\|acpi_create_madt_lapic_nmi\|acpi_create_madt\|acpi_create_madt_lapics\|acpi_create_madt_lapic_nmis\|acpi_create_madt_lx2apic\|acpi_create_srat_lapic\|acpi_create_srat_mem\|acpi_create_srat_gia_pci\|acpi_create_mcfg_mmconfig\|acpi_create_srat_lapics\|acpi_create_srat\|acpi_create_slit\|acpi_create_hmat_mpda\|acpi_create_hmat\|acpi_create_vfct\|acpi_create_ipmi\|acpi_create_ivrs\|acpi_create_crat\|acpi_create_hpet\|acpi_write_hpet\|generate_cpu_entries\|acpi_create_mcfg\|acpi_create_facs\|acpi_create_dbg2\|acpi_write_dbg2_pci_uart\|acpi_create_dmar\|acpi_create_dmar_drhd\|acpi_create_dmar_rmrr\|acpi_create_dmar_atsr\|acpi_create_dmar_rhsa\|acpi_create_dmar_andd\|acpi_create_dmar_satc\|cpi_dmar_\|acpi_create_\|acpi_write_hest\|acpi_soc_get_bert_region\|acpi_resume\|mainboard_suspend_resume\|acpi_find_wakeup_vector\|ACPI_S\|acpi_sleep_from_pm1\|acpi_get_preferred_pm_profile\|acpi_get_sleep_type\|acpi_get_gpe\|permanent_smi_handler\|acpi_s3_resume_allowed\|acpi_is_wakeup_s3\|acpi_align_current\|get_acpi_table_revision' -- src/) |grep "<" Change-Id: Iaa85a16d83bafb00a6e77371dc36f574a88030f7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-01superio/winbond/w83627hf/acpi: Replace LNot() with ASL 2.0 syntaxFelix Singer
Replace `LNot (a)` with `!a`. Change-Id: I9f08cc180614e7d966256b2944745b0bc1d29865 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-01superio/winbond/w83627hf/acpi: Replace LOr() with ASL 2.0 syntaxFelix Singer
Replace `LOr (a, b)` with `a || b`. Change-Id: I96cd391f1bdeea0c7e0c4a71c225a3e6925b4c6b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-01superio/winbond/w83627hf/acpi: Replace LAnd() with ASL 2.0 syntaxFelix Singer
Replace `LAnd (a, b)` with `a && b`. Change-Id: I66aedbab79d6b0d8e727d19b86458789a09889a8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60573 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-31superio/winbond/w83977tf/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b, c)` with `c = a + b`. Change-Id: I8028497d89a504d9bb277de5c0247e324e4cd608 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-30superio/winbond/w83627hf/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Subtract (a, b, c)` with `c = a - b`. Change-Id: Idd97e662ec4be7092a655bc298dffb6d826bc497 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-11-27superio/smsc/sch5545: Disable PS/2 lines isolation during initMichał Żygowski
Disable PS/2 data and clock isolation in order to properly initialize the PS/2 keyboard and mouse in payload/OS. These bits are set by OS via ACPI and can survive S5 state. It is necessary to clear them after an ungraceful shutdown in order to perform PS/2 controller initialization e.g. in SeaBIOS. TEST=PS/2 keyboard can always be successfully initialized in SeaBIOS on Dell OptiPlex 9010 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iac6be095c996b357b5d4e8d75199f94a89bf73e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59673 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-27superio/smsc/sch5545: Clear PMEs in the early initMichał Żygowski
Disable PMEs and clear global PME status to avoid undesired wakeups or hangs in later stages. These bits are set by OS via ACPI can survive S5 state so it is necessary to set them back to defaults after an ungraceful shutdown. TEST=Dell OptiPlex 9010 does not hang anymore after ungraceful shutdown when configuring GPE0_EN register in southbridge LPC init Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I790cac3ce1101565b64ed54d9c6b50f5e9aa4cf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59524 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-04superio: Replace bad uses of `find_resource`Angel Pons
The `find_resource` function will never return null (will die instead). In cases where the existing code already accounts for null pointers, it is better to use `probe_resource` instead, which returns a null pointer instead of dying. Change-Id: Ic6e28add78f686fc9ab4556eddbedf7828fba9ef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-05src/soc to src/superio: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-29superio/nuvoton/nct6776: Correct the definition of NCT6776_GPIOBASEBill XIE
NCT6776's data sheet does say that the virtual LDN of GPIO base should be 0x308, and most mainboards using it usually correctly config it in devicetree.cb under the path 2e.308, but in nct6776.h it used to be defined as 8 from the beginning (an ancient commit 1e3a22649a9, lately revived in commit f95daa510d6), identical to the LDN of WDT, which eliminates the definition of value 2e.308, and makes related resource allocations unable to take effect. (in log we can find "PNP: 002e.308 missing read_resources" if 2e.308 is enabled and assigned with resources) In this commit, NCT6776_GPIOBASE is set to a value consistent with the data sheet. With this commit, resources under 2e.308 of NCT6776 can be allocated successfully. Change-Id: I604bad7ab34a8f57262fdec508e5952cf8eabf1c Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-06src: Retype option API to use unsigned integersAngel Pons
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-04-28superio/nuvoton/npcd378: Fall back to non-negative valueAngel Pons
This change is needed to update the option API to use unsigned integers. The CMOS option system does not support negative numbers. So, adjust the call to get_int_option() to use 3 as fallback instead of -1. Change-Id: I46c5f5c6f47f99379cbafc0d60258b99dc512e9d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-21superio/nuvoton/npcd378: Fix `psu_fan_lvl` optionAngel Pons
If the option is successfully read from CMOS, the code overwrites its value with 3. Fix this issue and use the new get_int_option() function. Change-Id: I287a348da6ece78376d9c38e96128041752b032e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-21superio: Use get_int_option()Angel Pons
Change-Id: Ia46b622c52f98d4cc5fb7d9b02e2aeb366ef3915 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-22acpi/acpigen.h: Add more intuitive AML package closing functionsJakub Czapiga
Until now every AML package had to be closed using acpigen_pop_len(). This commit introduces set of package closing functions corresponding with their opening function names. For example acpigen_write_if() opens if-statement package, acpigen_write_if_end() closes it. Now acpigen_write_else() closes previously opened acpigen_write_if(), so acpigen_pop_len() is not required before it. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-13superio/smsc/sch5545: Add missing <types.h>Elyes HAOUAS
Add needed but missing <types.h>. Change-Id: I16c6a86e8c8863a8e16a63a379484c2b47d5185e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-11src/superio: Fix typo in commentElyes HAOUAS
Change-Id: I2e5cac310af824eb9756b2aa9459239e0b5784da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-29superio/nuvoton/common/Kconfig: Remove HWM configFrans Hendriks
lint-008-kconfig reports unused symbol SUPERIO_NUVOTON_COMMON_HWM. Remove SUPERIO_NUVOTON_COMMON_HWM. BUG = N/A TEST = N/A Change-Id: Ifad73f9ca4659e7b981a94c1e002e129d1b3388d Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-27src/superio: trim and move Makefile.inc, instead use wildcard matchesIdwer Vollering
Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: If77d59485451c77dcea752bc4fe0dfadba8fec45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48900 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03src: Remove redundant use of ACPI offset(0)Elyes HAOUAS
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset" example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, } We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-18superio/smsc/sio1036: Support 16-bit IO port addressingNikolai Vyssotski
SMSC/Microchip 1036 can be strapped to 4E/4D and 164E/164D so make source code support 16 bits addressing. Change-Id: I2bbe6f5b6dbd74299b34b0717e618dc736e7ad6f Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-19superio/nuvoton: Factor out equivalent Kconfig optionAngel Pons
There's no need to have multiple Kconfig symbols which do the same thing. Introduce `SUPERIO_NUVOTON_COMMON_COM_A` and update boards to use the new symbol. To preserve alphabetical order in mainboard Kconfig, place the new symbol above the Super I/O symbol (instead of below). Change-Id: Ic0a30b3177a1a535261525638be301ae07c59c14 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46522 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19superio/nuvoton: Correct NCT6791D COM A mux toggleAngel Pons
Bit 6 of global CR 0x2a toggles the mux for COM B. Bit 7 works just like on the other two Nuvoton Super I/Os, so fold the conditionals together. Change-Id: I8cebe35587ae68cac93ed392342662678621efd6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-17superio: Add newline to log message about disabled mouse controllerPaul Menzel
A newline is missing at the end of the informational message. PNP: 002e.5 init nct5572d_init: Disable mouse controller.PNP: 002e.5 init finished in 0 msecs PNP: 002e.307 init Change-Id: Ic73ed97be0993637be1e97040784d5a8e70a22ae Fixes: 6ff1078990 ("superio: Log if mouse controller is disabled") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-17superio/nuvoton: Only set bit 7 of global CR 0x2a for COM APaul Menzel
Currently, when selecting SUPERIO_NUVOTON_NCT*_COM_A, the whole global control register 0x2a is written to 0x40. CR 0x2a defaults to 0xc0, so indeed bit 7 is cleared, but the device early init code might have set other bits in that control register, so setting it to 0x40 might override already set bits. So, only clear bit 7 and leave the other bits untouched. Fixes: f95daa510d ("superio/nuvoton: Add back Nuvoton NCT6776 support") Change-Id: I9ded9dab3985c4c8e5c45af354ef44af482e18c2 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-13superio/nuvoton/common: Collapse two if statementsPaul Menzel
There are more devices requiring this code, so avoid duplicating the if block over and over. Change-Id: Ib4f787e3c883b1fec941de77bc8e19ccf0d5224c Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45970 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12superio/smsc/sch5147/acpi: Convert superio.asl to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I509b76dbdbdee8a6287fc7d877c9f6e3c6a9068b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12superio/smsc/sio1007/acpi: Convert superio.asl to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I9cca957104620e8fd4717d9bb77efa5a2c93b446 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12superio/ite/it8772f/acpi: Convert superio.asl to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I9a4d7ddd39800f07300d3b22b02924b696917f28 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12superio/smsc/mec1308/acpi: Convert superio.asl to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I7d15dbb90bbf910cdfd59d67fa4d9ca41420b8d9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12superio/fintek/f81803a/acpi: Convert superio.asl to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ia7072112a1add1de9c3fb348bc70dbd404337819 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45989 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12superio/winbond/*/acpi: Convert superio.asl to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I67e08a1099e41acb7031469069d9eddb274f7735 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45994 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22superio/ite: Distinguish between chips for PECI readingsMichael Büchler
Some chips can read external temperature sensor values only to TMPIN3. These use EC register 0x55, bit 7 to enable that. This patch adds support for this. It is called "old PECI" by lm_sensors [0]. Other chips can read to any TMPIN[1-3] which is configured in EC register 0x51 like the other temperature sources. This was the only supported method. This patch adds a Kconfig option to indicate this variant. This patch was tested on an Acer Aspire M3800 which has an IT8720F that reads the CPU temperature via PECI. It allows the automatic fan control feature of the Super I/O to work. Overview of support per chip in the coreboot tree, determined from reading the publicly available datasheets or lm_sensors, if noted: Old PECI: * IT8718F * IT8720F * IT8781F, IT8782F, IT8783E/F Normal PECI: * IT8721F (exception: no PECI to TMPIN2) * IT8728F * IT8772E (uses separate code in coreboot, not superio/ite/common) * IT8786E * IT8613E, IT8623E (lm_sensors) [0] Linux kernel 5.4.48, drivers/hwmon/it87.c Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: Iab7115852437d46c9b1269bba61ffcf680fe5a6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-18superio/nuvoton: Inline `nuvoton_hwm_select_bank`Angel Pons
There's no need to place a single-line function in its own compilation unit, and then guard it behind a Kconfig symbol. This also allows using this function in stages other than ramstage. Change-Id: I103a4ea4cef24844d382854c9358bbb37d229e04 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42130 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17src: Remove redundant <device/pnp_type.h>Elyes HAOUAS
When <device/pnp.h> is needed, it is supposed to provide <device/pnp_type.h>. Change-Id: I0e479e2abdb6cfb8633840db2222ce5397fe7d55 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45403 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17src: Remove redundant <device/pnp_def.h>Elyes HAOUAS
When <device/pnp.h> is needed, it is supposed to provide <device/pnp_def.h>. So remove redundant <device/pnp_def.h> includes. I'll remove also <device/pnp_type.h> in a separate patch. Change-Id: Ib9903ae456c32db4ba346020659c17c27a939e89 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14src/superio: Remove unused <device/pnp_def.h>Elyes HAOUAS
Change-Id: I835e8786b84ec16889fd08f566328bc7a0a60c90 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11src/superio: Use 'PNP_IDX_*' macros instead of magic numbersElyes HAOUAS
Change-Id: I2f8d6d9e8b6e84bb6c2b4e73b0fbeca476130d05 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-08-31superio/winbond/wpcd376i: Resurrect the driverSamuel Holland
This SuperIO chip is used on the Intel DQ45EK mainboard. Restore the driver that was deleted in commit d3a1a4171ee9 ("src/superio: Remove unused superio chips"). Changes from the previous version include: - Replacing the early serial implementation with Winbond common code, - Replacing the license boilerplate with SPDX headers, and - Removing unnecessary header file references. Change-Id: I0ff1a63c47d5dff2599c83a1cebe1ac5ff2136b1 Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-24src/superio: Drop unneeded empty linesElyes HAOUAS
Change-Id: I3fd0cc00f32fa073cb2a6faf2802acdbe7db592c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44614 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21superio/ite: delay PWRGD3 during resumeMichael Büchler
According to the IT8728F datasheet it is possible to add an extra delay between 3VSBSW# being set and PWRGD3 being set during resume from Suspend-to-RAM. This is enabled in the special function selection register, the default being 0. This is also useful for the IT8720F although this chip does not have the PWRGD3 output. On the corresponding pin it has PWROK2, which the setting then seems to apply to. The datasheet for the IT8720F marks the corresponding bit as reserved, but the vendor BIOS of an Acer Aspire M3800 sets it anyway. Without setting the bit, coreboot fails to resume from S3. Oscilloscope measurements have shown that setting the bit increases the delay between 3VSBSW# being set and PWROK2 being set from around 1 us to 140 ms. The actual use of PWROK2 on the board design is unclear - the only destination it seems to reach is a pin header near the SuperIO marked as "GPIO1". Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: I51cbf2470dc2b840a647a20090acb5a0cf4f4025 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-08-18src: Remove unused 'include <delay.h>'Elyes HAOUAS
Change-Id: I6afea5c102299e570378a1656d3dcd329a373399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44093 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-14superio/ite/it8728f: Correct Kconfig selectionsMatt DeVillier
Per the datasheet and the it87 kernel driver, the IT8728F supports both 5 fans (vs 3) and use of a single 7-bit register for the PWM slope (5 bits in closed-loop mode). Change-Id: I3d1e6f5030f18d2c8ff533965ae4718be0f3c279 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-08-14superio/ite/common: Add support for closed-loop modeMatt DeVillier
Add support for tachometer closed loop mode, and programming of initial RPM vs initial PWM value. Change-Id: Idff29331c979f8518021103b6f8d19e75e657e3a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-08-13superio/*/Makefiles: Remove non-existing directory inclusionElyes HAOUAS
Change-Id: I080f5b67c6e555fcc025ec11a1d15dddfe3a546d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-10superio/ite: allow 24 MHz clock for external sensor interfaceMichael Büchler
The interface selection register of the environment controller (EC) gives the choice between "Internal generated 32 MHz" and "24 MHz" for the "SST/PECI Host Controller Clock Selection". Previously the chip was always configured for the 32 MHz clock. Add an option that can be set from devicetree.cb to allow using the 24 MHz clock. Without this setting the automatic fan control on an Acer Aspire M3800 was slow to respond to temperature changes. Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: Ib2bce10a828fb4a7d837f6c5f5b1d00cc51be0ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/44166 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-10superio/ite: configure EC for fans to full at thermal limitMichael Büchler
This applies to the automatic fan control mode of the environment controller (EC). Previously the affected bit was always cleared while the default value is 1 according to datasheets. Add a variable that can be set per mainboard in devicetree.cb. In the IT8783E datasheet that bit is marked as reserved. Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: Ie74102ac0d54be33558c161c9c84594d121772b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-24superio/common: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects dereferencing a pointer that might be "NULL" when calling report_resource_stored. Add sanity check for dev to prevent NULL pointer dereference. Found-by: Coverity CID 1419488 Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I03efad87ba761e914b47e3294c646335cfbaed24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-19sio/nuvoton/common/early_serial.c: Guard serial enableAngel Pons
If CONSOLE_SERIAL is not set, do not reconfigure the UART LDN. Otherwise, SerialICE stops working when the UART LDN is disabled. Change-Id: Ie3113e6b7b830dfdddc4d7709f00719f29e094bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-12superio/nuvoton: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects dereferencing a pointer that might be "NULL" when calling acpigen_write_scope. Add sanity check for scope to prevent NULL pointer dereference. Found-by: Coverity CID 1420207 Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Icc253c63aadef1c0ecb116a38b608f64f80abc79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-16superio/winbond/w83977tf: Add suspend related fieldsKeith Hui
Add two fields for the ACPI logical device to the ACPI code. They are used for taking asus/p3b-f board out of suspend by keyboard or mouse. Change-Id: Icaadfea6a4dce7a2d665e8d89a024359975f8b2c Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41096 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08superio/nuvoton/nct6776: Reflow `pnp_dev_info` arrayAngel Pons
Each PnP device now fits in a single 96-character line. With BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ice65ce2504877c40962de7c26e01529d53d75c8e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-02superio/nuvoton/nct6779d: Open some LDN config registersKeith Hui
The porting of Asus P8Z77-M mainboard required changing certain Super I/O configuration registers that were ignored in devicetree.cb because they aren't listed as resources. Add the declaration so they can be changed. This change is nowhere near enough as the current structure is insufficient to allow changing configuration registers in the 0xE? range, which this board also needs. TEST=Changes to config regs 0xf4, 0xf5 in LDN 9 are reflected when inspected using superiotool -d. Change-Id: Ia31aafda3fa9423d516b5d839ef5265e8e8ccdd2 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-26superio/ite/Makefile.inc: Add it8613eAngel Pons
This Super I/O was not being built at all. Correct that. Change-Id: Id053fa919cac7b2df6a6fc45aae5e34a0dc8c0ae Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-20superio/winbond/w83977tf: Scope UART configuration defines more locallyPatrick Georgi
By undefining the configuration after use we're sure that nobody else comes to depend on it without us noticing. Change-Id: I7c5cfd58be643d6431989fc69cf3b397920590b9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-19superio/winbond/w83977tf: Fix iasl warningKeith Hui
The common PnP serial port DSDT code is intentionally included twice for two serial ports with different LDNs. Undefine LDN and the PM register name before redefining for second serial port so iasl doesn't complain. Change-Id: I031905479c66698fb01da028e3f37d923396d2d9 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41095 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-16superio/smsc/sch5545: add support for SMSC SCH5545Michał Żygowski
The SMSC SCH5545 is very similar to the publicly available datasheet for the SCH5627. TEST=use PS2 keyboard and mouse, serial port, runtime registers and Embedded Memory Interface on Dell Optiplex 9010 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If8a60d5802675f09b08014ed583d2d8afa29fc04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40350 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13src/mainboard: Remove unused 'include <stdlib.h>'Elyes HAOUAS
Found using following commande: diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l ' memalign\|malloc\|free' -- src/) |grep -v vendorcode |grep '<' Change-Id: Ib2ee840a10de5c10d57aa7a75b805ef69dc8da84 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41241 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11superio/winbond/w83977tf: Only list IR logical device if neededKeith Hui
Really old versions of W83977TF Super I/O had an IR logical device, but is no longer the case. It does not exist in the newer W83977EF version, installed in some Asus P2B family boards, and served by this same code. Add a config option on the off chance we may see board with it (as if we would) and don't include this device unless it is set. Saves us from the need to declare a not-present device off and/or extraneous PNP device errors about a not-present device. Change-Id: I761ebc41f1735a03e768339a68ca139167edc095 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41004 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-05superio/fintek/f81216h: Drop supportKeith Hui
No mainboards use this anymore. Change-Id: I2d58d73eca0be1f4daf9106a1258274486f803a5 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-29superio/aspeed/common: Add early configure functionsBryantOu
Add LPC read/write functions for access aspeed's memory, also create config data table to config memory and SIO. These functions are used at early stages to configure devices. Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com> Change-Id: Ib59c29a042b2c7bf196b8a5bd5218704d8075855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40483 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to acpi_fill_ssdt()Furquan Shaikh
.acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10Drop unnecessary DEVICE_NOOP entriesNico Huber
Providing an explicit no-op function pointer is only necessary for `.read_resources` and `.set_resources`. All other device-operation pointers are optional and can be NULL. Change-Id: I3d139f7be86180558cabec04b8566873062e33be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31superio/fintek: Improve code formattingElyes HAOUAS
Change-Id: I5ae2a2da1994fcc587540586d7404ebf18eb2ca0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-31superio/{acpi,common}: Improve code formattingElyes HAOUAS
Change-Id: I879ac7b558781d559a65c97fc8b914ecc4ad3f0d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-31superio/ite: Improve code formattingElyes HAOUAS
Change-Id: I014659aaddeb9fa2d5c3c3583e9379be4f9db69b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39929 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-03 11:03:53 +0000