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The implementation of wpcd376i in coreboot is based on the
superiotool output which apparently was incorrect. This
patch refines the implementation to match the datasheet.
Change-Id: I0108e912dc4f603276074f0999c6d3146c3b13f9
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/27857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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By defining SUPERIO_KBC_PS2M, ACPI code is added to show the PS/2 mouse.
This has been tested on an ASUS P8H61-M LX with Linux 4.9.110 and
4.17.8. In each case, the PS/2 mouse works automatically, whereas it was
not detected before.
Change-Id: I7983f85b3fd23547950f1f75a81bbca63c63d52b
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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When compiling for the ASUS P8H61-M LX, IASL 20180531 emits the
following remark: "Control Method should be made Serialized (due to
creation of named objects within)". Making the appropriate methods
Serialized eliminates these remarks.
Change-Id: I8e95d9a00a629a2f904c79b78fac20810327ed37
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27796
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Exposing the parallel port via ACPI causes Linux to automatically detect
the parallel port and load the appropriate modules. Tested on an ASUS
P8H61-M LX with Linux 4.9.110 and 4.17.8.
However, no parallel port device has been tested.
Change-Id: I2529a074e24433d093ad0650a45c7b29238620f3
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The constant used in the ACPI code is NCT6776_SHOW_KBC, so update
the comments to reflect that.
Change-Id: I9ba69384866088f84a516557d76864104a024968
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch makes it possible to enter the config mode of the super IO chip, so
that changes can be made to the configuration registers.
Change-Id: I7e31eaf217b3af2226c1e7d2f14f2ef7b0d7ddbe
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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The pnp ops struct is already passed to the pnp_enable_devices function and it
is used if no override is supplied in the elements of the pnp_info struct array
Change-Id: I4311834f3970bd3471f2f5a73ca7da3c03936d37
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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The pnp ops struct is already passed to the pnp_enable_devices function and it
is used if no override is supplied in the elements of the pnp_info struct array
Change-Id: I14dbeda9832a25116cf53c36197615e9d02d5134
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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The pnp ops struct is already passed to the pnp_enable_devices function and it
is used if no override is supplied in the elements of the pnp_info struct array
Change-Id: I42469c844074db57071d0191d12d8fd64f462672
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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The pnp ops struct is already passed to the pnp_enable_devices function and it
is used if no override is supplied in the elements of the pnp_info struct array
Change-Id: I5bd525532c01b3b9f7ddbc8eab42caa8b7f30795
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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The pnp ops struct is already passed to the pnp_enable_devices function and it
is used if no override is supplied in the elements of the pnp_info struct array
Change-Id: Ic6387032e043b6ad9e9ceefd2fcc1cdf843e2989
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Configure SuperIO on shutdown to keep devices enabled, set green LED
to fading on sleep and normal on wake.
Add SSDT to write LDN4 IOBASE addresses stored in devicetree.cb.
Tested on HP8200:
* Wakes from power button or USB keyboard.
* LED is fading
Change-Id: I2035249a39616aa2d87bd93f9e49c70d231546cc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Based on vendor ACPI code.
Change-Id: I4d6785efb9d18953042775e7164710ef3c041ed5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Pass the address of the chip-specific ops struct instead of the one of
the generic pnp_ops struct to the PNP device enable function.
This allows the removal of the LDN-specific ops overrides which is also done in
this patch.
Change-Id: I0c820254e97e3f80470d148552af06940e147b74
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/23008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Pass the address of the chip-specific ops struct instead of the one of the
generic pnp_ops struct to the PNP device enable function.
This allows the removal of the LDN-specific ops overrides which is also done in
this patch.
Change-Id: I16e485494e448ae02e0a7b9e21b90ddbb1a53a4b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/23007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Pass the address of the chip-specific ops struct instead of the one of the
generic pnp_ops struct to the PNP device enable function.
This allows the removal of the LDN-specific ops overrides which is also done in
this patch.
Change-Id: I5f03a4064778c419f4b9c50e70db1296addf6c9e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/23006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The pnp ops struct is already passed to the pnp_enable_devices function and it
is used if no override is supplied in the elements of the pnp_info struct array
Change-Id: I18345d7cc50a7d46cb15584dfb54df28e8534f81
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I1a8fc34aaaf42514c8af97ab155ff2712e7a5448
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/23009
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I2829e4cb1445f8412f57da10fda6b92c92e56ea0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Implement method to access the SuperIO's harware monitor (HWM) IO space.
Set the PSU fan using a new CMOS option psu_fan_lvl. Add the CMOS option
to all board that use NPCD378. In case no CMOS is set use the default
fan level 3.
The HWM space can be written to at any time, but the SuperIO has to be
notified that a write is ongoing. After clearing the write-lock bit all
changes are applied at once.
Tested on HP Compaq 8200 SFF.
Change-Id: I56ce7ad1df88638589a577b8a09d5d775557887b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26050
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Program the Super I/O to turn the machine on or restore its power state
when AC power is restored.
Based on code from src/superio/nuvoton/nct5572d/superio.c.
Change-Id: I1f3432f43b0784c3696bf1d7233b83d3a203af20
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/25463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The NPCD378 can be found on at least:
* HP Compaq 8200
* HP Compaq 8300
The datasheet is not publicly available, as HP implements lots of
custom hardware. Add basic support for it, based on HP Compaq 8200.
The first eight LDNs seem to be standard nuvoton compatible, except for
LDN4, which is used to control front LED and power in ACPI S3.
LDN8 provides access to HP's proprietary HWM which is accessiable at the LDN's
IOBASE with a size of 0x100 bytes.
The HWM consists of 16 pages with each holding 0xff bytes. The pages can be
selected by writing the page index to IOBASE + 0xff.
TODO:
Reverse engineer the HWM to support fan control.
WARNING:
The remaining LDNs have been guessed and might be wrong!
The serial has been tested and is working.
Change-Id: Ib497fd41b88e9c159eeeffa69bc2bfdccee9cb38
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25384
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Copies the common/env_ctrl support code from the it8728f driver.
Tested on an ASUS AM1I-A using Linux 4.16.7-gentoo as payload,
and booting userspace without a kexec call.
Prior to this change, an error was given during boot:
it87 it87.656: Detected broken BIOS defaults, disabling PWM interface
After this change, the message is gone, and PWM fan control works
through the /sys/class/hwmon interface.
Change-Id: Id97c4ec19562e7c78308c5afe6ff7c938922c9e7
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26224
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add device tree options to enable beeps when exceeding temperature,
voltage, and fan limits. As of this commit, setting voltage and fan
limits is not implemented.
Change-Id: I57ce622ee4498b75f00e678c2e6d72e499925bce
Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/22141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i3100
southbridge/intel/i3100
superio/intel/i3100
cpu/intel/socket_mPGA479M
Mainboards:
mainboard/intel/truxton
mainboard/intel/mtarvon
mainboard/intel/truxton
Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This change adds basic support for the SuperIO chip ITE IT8623E.
Due to the lack of a datasheet, defaults are shown as "not available (NA)"
in superiotool's register dump. LDNs defined in it8623e.h are
definitely correct and working as expected.
Change-Id: I05832c4db7ab59541337f11200640316376e792e
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/23001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This patch makes it possible to set the "Temperature Sensor Type Register"
at index 6Bh from the devicetree, allowing the use of thermistors instead of
BJT type sensors.
Register documentation (from page 60 of the F71869 datasheet):
6.6.25 Temperature Sensor Type Register - Index 6Bh
Bit 7-4: reserved
Bit 3: T3_MODE (0: thermistor, 1: BJT [default])
Bit 2: T2_MODE (0: thermistor, 1: BJT [default])
Bit 1: T1_MODE (0: thermistor, 1: BJT [default])
Bit 0: reserved
Change-Id: I6af0d93061ec49aec7a9181cdf7affd60fbdca73
Signed-off-by: Renze Nicolai <renze@rnplus.nl>
Reviewed-on: https://review.coreboot.org/22935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add ACPI declarations to be incorporated into ACPI tables for
mainboards with this super I/O.
Tested on Intel NUC DCP847SKE, Linux 4.13.14.
Change-Id: Idb76b2e99e90a213e2695efc1afd4fa9069c134f
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This fixes the bug that the LDNs on the affected SIO chips didn't get
configured, since the config mode wasn't entered.
Change-Id: Ic468847571e164e4e1280428f08fc067b724464e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/23004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add ACPI declarations to be incorporated into ACPI tables for
mainboards with this super I/O.
Change-Id: If113807901619bc0f4250607546be415f9e5e45b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Currently, having a keyboard connected to the PS/2 controller of the
ASRock E350M1, after suspending and resuming the system, the keyboard
does not work anymore. A similar problem is documented in commit
448e3863 (drivers/pc80: Add PS/2 mouse presence detect) [1].
There is no reason to not disable the controller during resume. Also,
that way, the PS2 ASL method does not need to be overriden.
[1] https://review.coreboot.org/13165
TEST=Resume system, and notice PS/2 keyboard works.
Change-Id: I51dc446861120f80bc9ffc4cc54b86e317d99689
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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It’s useful to know, if the mouse controller is disabled or not, so
convert the comment to a log message.
Change-Id: Ic3f7d5b7b98cf8c258a6a601f4a44ce403f4a576
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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These macros, broken since day one, should CreateByteField instead
of CreateWordField. Without the fix, any ASLs that try to use it
will fail to compile with a "ResourceTag smaller than Field"
warning.
Change-Id: Ieeb509aece8836785998b23fdc805a747d40a77a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Instead of setting "peci_tmpin" in the devicetree, THERMAL_PECI is now
a mode of TMPIN like THERMAL_RESISTOR and THERMAL_DIODE. Since the logic
to set temperature offsets and limits is in the function that sets
thermal modes, it makes sense to treat PECI as yet another mode.
As of this commit, there are no boards that actually use peci_tmpin from
ite/common. There are three boards that have a similar device tree
option, but those boards use it8772f, which implements all superio
functions on its own.
The first user will probably be Gigabyte GA-Z77-DS3H.
Change-Id: I39da50c124ad767f8681302733cf004622975e81
Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/22076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add devicetree options to set temperature limits that are used to alarm
user when temperature exceeds defined values.
Audio alerts by superio are not implemented yet, but since limits are
visible to userland, some software might use them as is. For instance,
lm-sensors displays "ALERT" when temperature exceeds limits.
Change-Id: I56e041fb78f518d6a9640dc2b3985459991242b9
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add a devicetree option to set temperature adjustment registers
required for thermal diode sensors and PECI. However, this commit does
not have the code needed to make PECI interface actually use these
registers. It only applies to diodes.
As a temporary workaround, one can set both THERMAL_DIODE and peci_tmpin
to the same TMPIN, e.g. TMPIN3.mode="THERMAL_DIODE" and peci_tmpin="3".
PECI, apparently, takes precedence over diode, so the adjustment register
will be set and PECI activated. Or simply use the followup patch, which
makes THERMAL_PECI a mode like THERMAL_DIODE.
I don't have hardware to test THERMAL_DIODE mode, but in case of PECI,
without this patch I had about -60°C on idle. Now, with offset 97,
which was taken from vendor bios, PECI readings became reasonable 35°C.
TEST=Set a temperature offset, then ensure that the value you set is
reflected in /sys/class/hwmon/hwmon*/temp[1-3]_offset
Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Once w83627hf_set_clksel_48() is unified into
winbond/common/early_init.c by /c/21331 (Unify w*_set_clksel_48()),
this file is no longer needed and can be dropped.
Build tested on select affected mainboards.
Change-Id: I6a5e27fdd48c6e002c3a39dc92fef77e85aea209
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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It is already using winbond_enable_serial(). Once
w83697hf_set_clksel_48() is unified into winbond/common/early_init.c,
this file is no longer needed and can be dropped.
Change-Id: I7424233b5d70e143721038493f194760f07346a1
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This function is identical throughout all Winbond superios in
the tree, so move it into superio/winbond/common/early_init.c,
renamed from early_serial.c because it now does more than just
early serial.
Change all affected mainboards to use the unified function.
Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Early serial for W83627[HF|EHG] superios are handled by
superio/winbond/common/early_serial.c. Remove code
thus deprecated.
Build tested on select affected mainboards.
Change-Id: Idad6e0281f7a272e184feff686ce1407825429c7
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Early serial init on this superio is done by
superio/winbond/common/early_serial.c and no board
currently references this instance anymore.
Change-Id: Iab8dd93663fc78ed0d8c6a5313bb6a1884d1a043
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This fixes indentation and whitespaces before opening parentheses.
Change-Id: I8940f712c0161419ee0c383b7bc9eb581967366e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This is a follow-on to the superio IS_ENABLED() patch:
https://review.coreboot.org/#/c/20351/1
Change-Id: I7d070e3964609947959de60e2686dfe59fe77e1c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ie9a7127b50db8dc9a2b543843ca4d815afe3d07e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The 'set' field was not used anywhere. Replace the struct with a simple
integer representing the mask.
initializer updates performed with:
sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04]? ?\}/0\1/g' \
src/ec/*/*/ec.c
sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04] ?\}/0\1/g' \
src/ec/*/*/ec_lpc.c \
src/superio/*/*/superio.c \
src/superio/smsc/fdc37n972/fdc37n972.c \
src/superio/smsc/sio10n268/sio10n268.c \
src/superio/via/vt1211/vt1211.c
src/ec/kontron/it8516e/ec.c was manually updated. The previous value for
IT8516E_LDN_SWUC appears to have been a typo, as it was out of range and
had a zero bit in the middle of the mask.
Change-Id: I1e7853844605cd2a6d568caf05488e1218fb53f9
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/20078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Myles Watson <mylesgw@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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This device is extremely similar to the IT8718F, so support is based on
existing support for the IT8718F. The CIR device is only detected by
Linux/Windows from the ACPI tables, so ACPI support is extended from the
IT8783E/F (for ACPI). This Super I/O is used on the Foxconn G41S-K.
Tested, working:
* Serial port 1
* Environment controller
- Temperature monitoring
- Voltage monitoring
- Fan control (automatic and manual)
* PS/2 keyboard and mouse
Appears, OS driver loads, but otherwise untested:
* Serial port 2
* Consumer IR
Untested:
* Floppy controller
* Parallel port
* GPIO
Change-Id: Ib9a6fe91a772d78f4d122a6c516feff8658ada0a
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/20026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Ifcbf95ffd6d13cae4e6864e0320ce6ce1cf3ae4d
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/20025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Id4a079d868c5c806c769b5559833566e8a6a8a71
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/20077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Some Super I/O PnP devices are detected by string matching the hardware
ID. Allow providing a custom HID to override the default generic one.
Change-Id: I7793b7d53c9d94667675f9dee63358521ac8c4be
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/20076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Some Super I/O logical devices have three I/O port ranges, such as the
GPIO on the IT8720F. Allow specifying a third I/O range. While here, fix
a typo in the I/O range description.
Change-Id: Idad03f3881e0fbf2135562316d177972f931afec
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/20024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Include <arch/io.h> since functions use types defined in there.
Change-Id: Iba6bcea4377359c15e3148062458186ee222b8e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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|
Change-Id: I05f768c67542770e65279a562c05225b84edca40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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This replaces the custom environment controller handling in the it8728
driver with the common library.
It also updates the two existing boards with hwm register settings in
their devicetree config so they better match their vendor BIOS fan
control settings.
Change-Id: Idf0c8908ba5ad6ff552b8302bffc638aa9052941
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/19293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This chip is similar to the Fintek F71869AD.
Change-Id: Iba3f3dadf2b15071981f52d0b08da7847354bd23
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18563
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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Current ACPI code for UARTs uses the PNP_DEFAULT_PSC macro for _PSC
(current power state) methods. Override it to `Return (0)` (i.e. cur-
rent state is D0) as the IT8783E/F doesn't have power management.
Change-Id: I3c858dde287dbf7e5fc0c20abb1fd374887acdde
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17791
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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This will be used by new Roda boards. Four UARTs and PS/2 keyboard and
mouse are exposed to ACPI. Since our boards only use the environment
controller part, most of the usual pnp interfaces are untested.
Change-Id: Ifeb0327ad115759411716f82585ace5ce55b8464
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17287
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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ITE super-i/o chips need a fourth byte and have a special register
to exit config mode.
Change-Id: Ic40873649d567b87d3a937f2bf068649e67715de
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17286
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Change-Id: I8cbfe49516e685c1b3e150b23f9fcac513f1f3dc
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17285
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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The purpose of this change is to enable serial output in
bootblock stage
Change-Id: I8e075f1e70d1a6598dfdc34931218f5af9637178
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/17359
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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The devicetree parameter already existed without being
used in the code.
Change-Id: I99dd8bc7a9b2f3509a115a130062d462a62e33fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17614
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: I25019c6323b6e9de2e0ce19325266bf3e8f2e309
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17581
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This is a stopgap for when you use SUPERIO_SMSC_SMSCSUPERIO and the
interrupt is unmapped at reset, but for whatever reason the chip is
inaccessible in smscsuperio/superio.c::enable_dev() and thus the
devicetree.cb IRQ information is not applied in ramstage and then
serial console output fails to work for more than the UART FIFO depth
in the OS.
Change-Id: I00998088975569516f7caeb7f4098b48fe437889
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/10807
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: I597ba3a03bd42c64d03137b10a3758d86b129029
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17452
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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The environment-controller entity is shared by many ITE super-i/o
chips. There are some differences between the chips, though. To cover
that, the super-i/o chip should select Kconfig options of this driver
accordingly.
The current implementation isn't exhaustive: It covers only those
parts that are connected on boards I could test, plus those that are
currently used by the IT8772F. The latter could be ported to use this
driver if somebody minds to test it.
Change-Id: I7a40f677f667d103ce1d09a3e468915729067803
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17284
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I5f88f34d1c040ac6ed413cfaf8ceb45a358c117c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17048
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: Ie2062672233141b6f34625e59cbb50238be0b5fa
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16726
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Revert commit 53552cc0 (Drop SuperIO nuvoton/nct6776),
removing the code as no other mainboard uses it.
The board Intel Saddle Brook uses this device, so add the
code back with minor adaptations.
Change-Id: I546879285ad8336e81798d0fbdf94f72e1fa61a2
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/16519
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Ibeab5e7fe0a9005e96934b3b43cfb247ef2e2340
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16615
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I8597d205ca84bee0171c3d45549a28b58a050529
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16433
Tested-by: build bot (Jenkins)
Reviewed-by: Antonello Dettori <dev@dettori.io>
|
|
All but ga-g41m-es2l/cmos.default had multiple final newlines.
ga-g41m-es2l/cmos.default had no final newline.
Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16361
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Antonello Dettori <dev@dettori.io>
|
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This moves the Kconfig from the Super I/O manufacturer folder
to the chip folder instead.
This makes new chip commits self-contained unit as
edits to the central Kconfig file are no longer required.
Change-Id: I7aee07919f2ae9204850c669e0ed3cb17d4de8cd
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/15973
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
|
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Pins for UART 3/4 are by default GPIO pins.
This patch sets the pins in UART mode.
Since UART 1/3 and 2/4 share the same interrupt line,
the patch needs to enable also shared interrupts.
Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P
Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html
Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15564
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This adds support for Nuvoton NCT6791D Super I/O chips.
Makes use of the common Nuvoton early_serial.c.
Based on the Datasheet supplied by Nuvoton.
Datasheet Version: January 8th, 2016 Revision 1.11
Change-Id: I027d33b85f0dc6ee50deebdccaecc74487eecb40
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/15967
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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Change-Id: Ib98c69de781d2b651ec168d03250cacc918c5c1f
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/14965
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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Certain mainboards require SuperIO pinmux configuration before
peripherals will become operational. Allow each mainboard to
configure the pinmux(es) of Winbond chips if needed.
Change-Id: Ice19f8d8514b66b15920a5b893700d636ed75cec
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/14960
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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Certain mainboards, e.g. the ASUS KGPE-D16/KCMA-D8, require
board-specific configuration changes to the SuperIO. Expose
the functions needed to enter and exit configuration mode
on Winbond devices.
Change-Id: Ic86651872ecafcfe1398201be2b0768bbe460975
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14891
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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The way this was implemented before was causing ACPI failures. There
was also a basic misunderstanding of what the AddressMax field was used
for. In this case, because it's a fixed address, it should be the same
as the AddressMin field.
Getting rid of the addition in the field solves the ACPI output problem.
Change-Id: Idec2bf0ed27ae694e98f141087cdf22401937178
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14343
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
|
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This resolves error messages of the form:
ERROR: device PNP: 002e.6 index 98 has no mask.
Change-Id: I6a368b902d051c8da6f74cbde54f5d12a3e52c2f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14272
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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The official spelling of Nuvoton is not all uppercase. Only the first
letter is uppercase. See the footer of the Nuvoton Web site.
Change-Id: I6ccd4194d7be0c89f8b332fcca5feb2420a4de1e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/5928
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Remove dependency on early_serial.c and instead use the
Super I/O's header to access the functions needed.
Also re-organize some of the superio code in order
to succesfully compile the rom.
Change-Id: I85a6f1352ae3b91c3c98e4d3fa0b90b87e02babc
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/13925
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Remove dependency on early_serial.c and instead use the
Super I/O's header to access the functions needed.
Change-Id: I9edf7fc2501aa832106dda9213e702dbcc1200b4
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/13887
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
|
On certain Super I/O devices, when a PS/2 mouse is not present on the
auxiliary channel both channels will cease to function if the
auxiliary channel is probed while the primary channel is active.
Therefore, knowledge of mouse presence must be gathered by coreboot
during early boot, and used to enable or disable the auxiliary PS/2
port before control is passed to the operating system.
This is added in commit 448e3863 (drivers/pc80: Add PS/2 mouse
presence detect).
Update the Nuvoton NCT5572D driver to flag the auxiliary channel as
disabled if no device was detected. The code is copied from the Winbond
W83667HG-A driver.
Note, the ACPI changes are not part of this commit.
TEST=Currently, on the ASRock E350M1, PS/2 does not work. With this
change, a PS/2 keyboard works fine in SeaBIOS, GRUB in MBR, and Debian
GNU/Linux Sid/unstable with Linux 3.19.
```
[ 1.185195] i8042: PNP: No PS/2 controller found. Probing ports directly.
[ 1.189110] serio: i8042 KBD port at 0x60,0x64 irq 1
[ 1.189133] serio: i8042 AUX port at 0x60,0x64 irq 12
[ 1.189970] mousedev: PS/2 mouse device common for all mice
```
Change-Id: I7f9be348d295e70437bef089d4c2173169f38459
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/13618
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
On certain Winbond SuperIO devices, when a PS/2 mouse is not
present on the auxiliary channel both channels will cease to
function if the auxiliary channel is probed while the primary
channel is active. Therefore, knowledge of mouse presence
must be gathered by coreboot during early boot, and used to
enable or disable the auxiliary PS/2 port before control is
passed to the operating system.
Add auxiliary channel PS/2 device presence detect, and update
the Winbond W83667HG-A driver to flag the auxiliary channel as
disabled if no device was detected.
Change-Id: I76274493dacc9016ac6d0dff8548d1dc931c6266
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13165
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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The KGPE-D16 and KCMA-D8 use a Winbond W83667HG-A SuperIO. While
the Nuvoton NCT5572D is effectively the same core, and a close
enough match to get things working initially, the W83667HG-A
has a different LDN mapping and several extra features that
require a separate support driver.
Clone the Nuvoton NCT5572D and modify according to the W83667HG-A
datasheet, version 1.4.
Change-Id: I707ba2e40a22d41cd813003d84a82cb20304f55b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13156
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This just updates existing guard name comments on the header files
to match the actual #define name.
As a side effect, if there was no newline at the end of these files,
one was added.
Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12900
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This continues what was done in commit a73b93157f2
(tree: drop last paragraph of GPL copyright header)
Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12914
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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- occured -> occurred
- accomodate -> accommodate
- existant -> existent
- asssertion -> assertion
- manangement -> management
- cotroller -> controller
Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12850
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Original-Signed-off-by: Ted Kuo <tedkuo@ami.com.tw>
Change-Id: I70d7b572e9ae030136a39fb6fa933f486d559aef
Original-Reviewed-on: https://chromium-review.googlesource.com/262832
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Commit-Queue: Ted Kuo <tedkuo@ami.com.tw>
Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12799
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Set up External Temperature to read via thermal diode/resistor
into TMPINx register by setting thermal_mode switch.
Original-Signed-off-by: Ted Kuo <tedkuo@ami.com.tw>
Change-Id: I0e8621b92faa5c6246e009d2f852c8d4db484034
Original-Reviewed-on: https://chromium-review.googlesource.com/260545
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw>
Original-(cherry picked from commit 973e2d393f2595b756f8aa20f6fbe3b6e045621a)
Original-Reviewed-on: https://chromium-review.googlesource.com/262340
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12798
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: Id6d50d4d6af31e43f851645f09383121755291f6
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12815
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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According to the PNP ISA v1.0a spec, config registers in the range of
0xf0 up to 0xfe are vendor defined and may be used for any purpose.
Config register 0xff is reserved and is defined as such.
Currently, only vendor specific registers 0xf0, 0xf1, 0xf4, and 0xfa
are able to be set using the PNP_MSCx bit flag masks.
This patch adds support for all 15 vendor specific config registers,
and updates the existing superio pnp_info to use them where appropriate.
Change-Id: Id43b85f74e3192b17dbd7e54c4c6136a2e59ad55
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12808
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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- Remove it8772f c includes
- Add a new LED API, it8772f_gpio_led
- Stumpy: using it8772f_gpio_led
BUG=chrome-os-partner:28232
BRANCH=Guado
TEST=emerge-guado coreboot chromeos-bootimage
Change-Id: I08de52515d3c1e7e85d1761c09a0cebffda7dda3
Signed-off-by: David Wu <David_Wu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/241813
Tested-by: David Wu <david_wu@quantatw.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: David Wu <david_wu@quantatw.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12797
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The SIO device needs to provide an _ADR object with the IO
address as well as the address in the OperationRegion.
ACPI provides two different Resource Descriptor Macros to describe the
I/O areas required for a device. The FixedIO macro is only valid for
10-bit IO addresses. Use the IO macro instead.
Thank you to recent IASL that allows for addition in the ASL file. :)
Fixes these warnings:
dsdt.aml 2276: Device (SIO) {
Warning 3141 - ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml 2390: FixedIO (0xa00, 0x34)
Warning 3060 - ^ Maximum 10-bit ISA address (0x3FF)
dsdt.aml 2394: FixedIO (0xa00, 0x34)
Warning 3060 - ^ Maximum 10-bit ISA address (0x3FF)
Lumpy now compiles its ASL tables with no warnings. Re-enable
Warnings as errors.
Change-Id: Id26e234eadaa3b966e8f769cb9f9fb7ea64fc9e3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12520
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This reverts commit 42444f6f53d47604d9a44c9e109b5717efaed74f.
Change-Id: Ifaaaad715d94c3c9ff365745aa2e6ee546924f4f
Reviewed-on: http://review.coreboot.org/12328
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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All boards using this SuperIO have been removed from the tree already.
Change-Id: I3c43a431d92d76b6ed3ec72b203d3e80925cadea
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12247
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The Intel i8900 Super I/O is similar to the previously
supported i3100.
Change-Id: I9a5b651cab35991c3c3e09fc4668d35ca2d221ba
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12169
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: York Yang <york.yang@intel.com>
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The Winbond WPCD376I is a desktop Super I/O often selected on
Intel mainboards. The support is similar to other Winbond and NSC SIOs.
Based on output from superiotool -d.
Change-Id: Ib4786b410b1d83606e8d79a9f686c14a5d25cadf
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12165
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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All boards using this SuperIO have been removed from the tree already.
Change-Id: I52847bc2fc16b27ac0de0bc7c847221b1e5cb744
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12245
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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While the actual pins behind these devices are not exposed on the chip,
the enable registers are implemented in hardware. Allow to turn these LDNs
off, like the vendor bios for asrock/e350m1 does.
Change-Id: I4d6d5a8de12b09095138cacbad62b2dfbbe54028
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12213
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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