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2020-03-31superio/winbond: Improve code formattingElyes HAOUAS
Change-Id: Ia63e21b957d89690f36929f9ffbe8a7bf8f0e84c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-31superio/winbond/{w83627hf,w83977tf}: Use macroElyes HAOUAS
Change-Id: I3ac8dd2ba089970a18b460769dfc3fabf9395709 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39907 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-29superio: Replace D1/D2 power states with D3Nico Huber
Spec says if any object to control the power state exists, at least D0 and D3 must be supported. And it seems Windows complains about the missing D3 support: https://ticket.coreboot.org/issues/257 Windows reported `*** STOP: 0x000000A5` with the first parameter `0x000000000000000D` (refers to a missing ACPI object) and the third parameter `0x000000003353505F` which is the name of the object in ASCII, little-endian (`_PS3`). Change-Id: Ifa28a7c56575848e76e4a1c542866413b4c44d50 Signed-off-by: Nico Huber <nico.h@gmx.de> Closes: https://ticket.coreboot.org/issues/257 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-10winbond/w83667hg-a: Disable mouse controller also during resumePaul Menzel
There is no reason to not disable the controller during resume. That way, no ASL is needed. Change-Id: I282a03647ee0958abb118fafe306abe5782db71c Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/22286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-30src/superio: replace license boilerplate with SPDXFelix Held
The authors from the header of the files are added in a previous commit. Change-Id: Iafeaafb9689c65bd2f5de3960097ec0d4c1009e7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38544 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09drivers/pc80/rtc: Separate {get|set}_option() prototypesKyösti Mälkki
Long-term plan is to support loading runtime configuration from SPI flash as an alternative, so move these prototypes outside pc80/. Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-13superio/*: Don't use conf_mode directlyPatrick Rudolph
Use the functions defined in device/pnp.h instead of using the conf_mode directly. This will make future refactoring easier. Change-Id: Ibb94d86b3ee861f44cded469ff58b545dd7311fd Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-05superio/*/*/acpi: Improve the readability of the IndexFieldElyes HAOUAS
Change-Id: I64fdcbcbbd54334c1c551bc1346c6000ea82c97d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-20superio: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Change-Id: I55e7b680e128f29a9fd549edfb676e6571330677 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-13src/superio: Remove unused superio chipsMartin Roth
These SIOs are not being used or tested by abuild, so remove them from the tree. The only 3 currently unused SIOs that don't get removed here have board ports in review. src/superio/fintek/f71805f src/superio/fintek/f71872 src/superio/intel/i8900 src/superio/ite/it8671f src/superio/ite/it8716f src/superio/nsc/pc87309 src/superio/nsc/pc87360 src/superio/nsc/pc87366 src/superio/nsc/pc97317 src/superio/smsc/dme1737 src/superio/smsc/lpc47b272 src/superio/smsc/lpc47b397 src/superio/smsc/sch4037 src/superio/smsc/sio1036 src/superio/via/vt1211 src/superio/winbond/w83697hf src/superio/winbond/wpcd376i Signed-off-by: Martin Roth <martin@coreboot.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I61d486d2c1e2b85eb292eaa78316c36e1735ebf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-08superio/winbond/w83627*: use hwm5_conf.h for HWM setupFelix Held
Change-Id: Id78042606f02e02035dc917d162d0c98c9de38a4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-04device/pnp: Add header files for PNP opsKyösti Mälkki
Change-Id: Ifda495420cfb121ad32920bb9f1cbdeef41f6d3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31698 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-07src: Remove unused include device/pnp_def.hElyes HAOUAS
Change-Id: Ibb7ce42588510dc5ffb04c950c4c8c64e9a2fa37 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-04superio/winbond/w83627ehg: Correct CR 0x2a commentElyes HAOUAS
Register 0x2a [Bit 1] is a PIN89, PIN90 function select for i2c Change-Id: I9231a68ec7e9a3130a6b6975544bf89ab09cb3e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06Kconfig: Unify power-after-failure optionsNico Huber
The newest and most useful incarnation was hiding in soc/intel/common/. We move it into the Mainboard menu and extend it with various flags to be selected to control the default and which options are visible. Also add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the boolean to int conversion into Kconfig: 0 - S5 1 - S0 2 - previous state This patch focuses on the Kconfig code. The C code could be unified as well, e.g. starting with a common enum and safe wrapper around the get_option() call. TEST=Did what-jenkins-does with and without this commit and compared binaries. Nothing changed for the default configurations. Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06superio/*: Link early initialization into bootblockArthur Heymans
This allows to set up the SuperIO in the C_ENVIRONMENT_BOOTBLOCK bootblocks. It is likely unnecessary to do this in verstage. This also renames COMMON_ROMSTAGE to COMMON_PRE_RAM. Change-Id: I3d999611baa1e79c79fe6b1f01822ebaa5f85daf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18{drivers,superio}: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
Change-Id: Ia42c1f8559667e7711fac919df8bfbee8455e3cc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-19src: Add required space after "switch"Elyes HAOUAS
Change-Id: I85cf93e30606bc7838852bd300a369e79370629a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Remove unneeded include <pc80/keyboard.h>Elyes HAOUAS
Change-Id: I0dcdfb1fa782c7936a19de11adcf17387f49d9db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-08-13superio/winbond/w83627hf: Remove unused valueElyes HAOUAS
Change-Id: I90d1997254f6766f4c61ff55449109adbdd783e3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-09superio: fix and extend pnp_info of wpcd376iStefan Tauner
The implementation of wpcd376i in coreboot is based on the superiotool output which apparently was incorrect. This patch refines the implementation to match the datasheet. Change-Id: I0108e912dc4f603276074f0999c6d3146c3b13f9 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/27857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-25superio/winbond: remove LDN-specific ops overridesFelix Held
The pnp ops struct is already passed to the pnp_enable_devices function and it is used if no override is supplied in the elements of the pnp_info struct array Change-Id: I4311834f3970bd3471f2f5a73ca7da3c03936d37 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-14src: Use of device_t is deprecatedElyes HAOUAS
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-12-02winbond/w83977tf: Add ACPI declarationsKeith Hui
Add ACPI declarations to be incorporated into ACPI tables for mainboards with this super I/O. Change-Id: If113807901619bc0f4250607546be415f9e5e45b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-11-30superio: Log if mouse controller is disabledPaul Menzel
It’s useful to know, if the mouse controller is disabled or not, so convert the comment to a log message. Change-Id: Ic3f7d5b7b98cf8c258a6a601f4a44ce403f4a576 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/22285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-09-21winbond/w83627hf: Drop early_init.cKeith Hui
Once w83627hf_set_clksel_48() is unified into winbond/common/early_init.c by /c/21331 (Unify w*_set_clksel_48()), this file is no longer needed and can be dropped. Build tested on select affected mainboards. Change-Id: I6a5e27fdd48c6e002c3a39dc92fef77e85aea209 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-21winbond/w83697hf: Drop early_serial.cKeith Hui
It is already using winbond_enable_serial(). Once w83697hf_set_clksel_48() is unified into winbond/common/early_init.c, this file is no longer needed and can be dropped. Change-Id: I7424233b5d70e143721038493f194760f07346a1 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-21superio/winbond/*: Unify w*_set_clksel_48()Keith Hui
This function is identical throughout all Winbond superios in the tree, so move it into superio/winbond/common/early_init.c, renamed from early_serial.c because it now does more than just early serial. Change all affected mainboards to use the unified function. Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-21superio/winbond/w83627*: Remove deprecated codeKeith Hui
Early serial for W83627[HF|EHG] superios are handled by superio/winbond/common/early_serial.c. Remove code thus deprecated. Build tested on select affected mainboards. Change-Id: Idad6e0281f7a272e184feff686ce1407825429c7 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-15superio/winbond/w83977tf: Drop early_serial.cKeith Hui
Early serial init on this superio is done by superio/winbond/common/early_serial.c and no board currently references this instance anymore. Change-Id: Iab8dd93663fc78ed0d8c6a5313bb6a1884d1a043 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-13device/pnp: remove struct io_infoSamuel Holland
The 'set' field was not used anywhere. Replace the struct with a simple integer representing the mask. initializer updates performed with: sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04]? ?\}/0\1/g' \ src/ec/*/*/ec.c sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04] ?\}/0\1/g' \ src/ec/*/*/ec_lpc.c \ src/superio/*/*/superio.c \ src/superio/smsc/fdc37n972/fdc37n972.c \ src/superio/smsc/sio10n268/sio10n268.c \ src/superio/via/vt1211/vt1211.c src/ec/kontron/it8516e/ec.c was manually updated. The previous value for IT8516E_LDN_SWUC appears to have been a typo, as it was out of range and had a zero bit in the middle of the mask. Change-Id: I1e7853844605cd2a6d568caf05488e1218fb53f9 Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Myles Watson <mylesgw@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-04superio/winbond/*/header: Include <arch/io.h>Arthur Heymans
Include <arch/io.h> since functions use types defined in there. Change-Id: Iba6bcea4377359c15e3148062458186ee222b8e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-12-07sio/acpi: Add more magic bytes to ENTER/EXIT_CONFIG_MODENico Huber
ITE super-i/o chips need a fourth byte and have a special register to exit config mode. Change-Id: Ic40873649d567b87d3a937f2bf068649e67715de Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17286 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-19winbond/w83627ehg: Remove unnecessary valueElyes HAOUAS
Change-Id: I5f88f34d1c040ac6ed413cfaf8ceb45a358c117c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17048 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-01sio/winbond/w83627dhg: Add ACPI function to control suspend LEDNico Huber
Change-Id: Ie2062672233141b6f34625e59cbb50238be0b5fa Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16726 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-09superio/*: Relocate Kconfig to chip folder.Omar Pakker
This moves the Kconfig from the Super I/O manufacturer folder to the chip folder instead. This makes new chip commits self-contained unit as edits to the central Kconfig file are no longer required. Change-Id: I7aee07919f2ae9204850c669e0ed3cb17d4de8cd Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/15973 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2016-05-29sio/winbond/w83667hg-a: Add pinmux defines for UART BTimothy Pearson
Change-Id: Ib98c69de781d2b651ec168d03250cacc918c5c1f Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/14965 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-05-29sio/winbond/common: Add function to configure pin muxTimothy Pearson
Certain mainboards require SuperIO pinmux configuration before peripherals will become operational. Allow each mainboard to configure the pinmux(es) of Winbond chips if needed. Change-Id: Ice19f8d8514b66b15920a5b893700d636ed75cec Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/14960 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-05-20sio/winbond: Expose enter/exit configuration state functionsTimothy Pearson
Certain mainboards, e.g. the ASUS KGPE-D16/KCMA-D8, require board-specific configuration changes to the SuperIO. Expose the functions needed to enter and exit configuration mode on Winbond devices. Change-Id: Ic86651872ecafcfe1398201be2b0768bbe460975 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14891 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-04-08superio/winbond/w83667hg-a: Set SPI device mask correctlyTimothy Pearson
This resolves error messages of the form: ERROR: device PNP: 002e.6 index 98 has no mask. Change-Id: I6a368b902d051c8da6f74cbde54f5d12a3e52c2f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14272 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-02-01drivers/pc80: Add PS/2 mouse presence detectTimothy Pearson
On certain Winbond SuperIO devices, when a PS/2 mouse is not present on the auxiliary channel both channels will cease to function if the auxiliary channel is probed while the primary channel is active. Therefore, knowledge of mouse presence must be gathered by coreboot during early boot, and used to enable or disable the auxiliary PS/2 port before control is passed to the operating system. Add auxiliary channel PS/2 device presence detect, and update the Winbond W83667HG-A driver to flag the auxiliary channel as disabled if no device was detected. Change-Id: I76274493dacc9016ac6d0dff8548d1dc931c6266 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13165 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29superio/winbond/w83667hg-a: Add support for W83667HG-ATimothy Pearson
The KGPE-D16 and KCMA-D8 use a Winbond W83667HG-A SuperIO. While the Nuvoton NCT5572D is effectively the same core, and a close enough match to get things working initially, the W83667HG-A has a different LDN mapping and several extra features that require a separate support driver. Clone the Nuvoton NCT5572D and modify according to the W83667HG-A datasheet, version 1.4. Change-Id: I707ba2e40a22d41cd813003d84a82cb20304f55b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13156 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-01-13tree: drop last paragraph of GPL copyright header from new filesMartin Roth
This continues what was done in commit a73b93157f2 (tree: drop last paragraph of GPL copyright header) Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12914 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07Correct some common spelling mistakesMartin Roth
- occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-09superio/windbond: Add WPCD376I deviceMarc Jones
The Winbond WPCD376I is a desktop Super I/O often selected on Intel mainboards. The support is similar to other Winbond and NSC SIOs. Based on output from superiotool -d. Change-Id: Ib4786b410b1d83606e8d79a9f686c14a5d25cadf Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/12165 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-14superio: Replace the indexed I/O functionsDave Frodin
Replace the multiple indexed I/O read and write functions with common functions. Change-Id: Idfe7a8784c28d51b3fbcb2f4e26beaa0b91741a8 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/10145 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2014-12-16Drop obsolete SuperIOs used by GX1 systems onlyStefan Reinauer
Drop two SuperIOs that were only used by GX1 systems, and are not used anymore. * winbond/w83977f * nsc/pc87351 Change-Id: I8a8eacb0f862b5d08ccfd87f8db503b0ab3c5700 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7118 Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-27superio/*/superio.c: Don't hide pointer types behind typedefsEdward O'Callaghan
Hiding pointer types behind 'typedef's is usually not a great idea at the best of times. Worse the typedef becomes an integer at different stages in Coreboot. Let us refrain from doing this at all. Change-Id: Ia2ca8c98bb489daaa58f379433875864f6efabc8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7136 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-10-27superio: Use 'pnp_devfn_t' over 'device_t' in romstage componentEdward O'Callaghan
The romstage component of Super I/O support is in fact written around passing a lower and upper half packed integer. We currently have two typedef's for this, 'device_t' and 'pnp_devfn_t'. We wish to make use of 'pnp_devfn_t' over 'device_t' as 'device_t' changes it's typedef in the ramstage context and so is really a conflicting definition. This helps solve problems down the road to having the 'real' 'device_t' definition usable in romstage later. This follows on from the rational given in: c2956e7 device/pci_early.c: Mixes up variants of a typedefs to 'u32' Change-Id: Ia9f238ebb944f9fe7b274621ee0c09a6de288a76 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6231 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2014-07-17superio,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: Ia452e22af9491c1681c859691eb4ac1868eeb938 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6282 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-31superio/winbond/w83627hf: Avoid .c includes in mainboardsEdward O'Callaghan
Move towards the removal of the superio model specific xxx_serial_enable implementation. Make remaining superio romstage parts link-time symbols and fix corresponding mainboards to match. The following mainboards remain unconverted as they are ROMCC: - mainboard/supermicro/x6dai_g - mainboard/supermicro/x6dhe_g - mainboard/supermicro/x6dhr_ig - mainboard/supermicro/x6dhr_ig2 and so block the final removal of w83627hf_serial_enable(). Special cases: - mainboard/supermicro/h8qme_fam10: Provide local pnp_ sio func Provide local superio pnp_ programming entry/exit functions as to avoid making superio implementation global symbols. Although this is not the proper/final solution, it does mitigate possible symbol collisions and allow for continued superio refactorisation. Change-Id: Iaefb25d77512503050cb38313ca90855ebb538ad Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5601 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-31superio/winbond/w83627ehg: Depreciate romstage componentEdward O'Callaghan
Part 1/2: These are actually not necessary if Super I/O support is properly utilized. Change-Id: I39b621e582f8d0762276d29492c91dce500f0665 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5870 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-28superio/winbond/w83627thg: Depreciate romstage componentEdward O'Callaghan
Depreciate the model specific early_serial.c romstage component for this Super I/O in favor of the recent generic winbond romstage framework. Change-Id: I22775dc9b6341c8994d21591b7176abe4dd99911 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5724 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-28superio/winbond/w83627uhg: Depreciate romstage componentEdward O'Callaghan
Depreciate the model specific early_serial.c romstage component for this Super I/O in favor of the recent generic winbond romstage framework. Convert dependent board to generic winbond serial init. Note the clock function is actually invalid since it never enters into PNP config mode to twiddle the register. Further, 48MHz is the default (page 9 of data-sheet) and so romstage.c need not do anything to the clock rate hence why it presumably works with this invalid function. Change-Id: I4706a1446c1b391b8390ac0361700ce6f15b9206 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5725 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-23superio/winbond/w83697hf: Depreciate romstage componentEdward O'Callaghan
Depreciate the model specific early_serial.c romstage component for this Super I/O in favor of the recent generic winbond romstage framework. Change-Id: I529c9cd1d8d63db3035b4828b3c3fc43911f49ce Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5727 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2014-05-13superio/*: Remove redundant chip.h headerEdward O'Callaghan
Change-Id: If7141112ea67071ee05c52f455c3b2496aa7e17e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5622 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13superio/*: Deal with some chip.h special casesEdward O'Callaghan
While backing out the empty pc80 keyboard struct we encountered some special cases where chip.h is used for other purposes. Deal with these cases. Change-Id: Ib11a46cfd14d050d5daa213623b9d8a401c06410 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5621 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13src/drivers/pc80: Remove empty struct keyboardEdward O'Callaghan
This is a empty struct that has propagated through the superio's & ec's but really does nothing. Time to get rid of it before it adds yet more cruft. However, since this touches many superio's at once we do this in stages by first changing the function type to be a pure procedure. Change-Id: Ibc732e676a9d4f0269114acabc92b15771d27ef2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5617 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-02superio/winbond/w83627thg: Remove w83627thg_enable_serial symbolEdward O'Callaghan
Remove model specific implementation, w83627thg_enable_serial, from romstage component of sio support. Change-Id: I8ef1de5ccccae5f4dba69dbdb939e7070d3cecfc Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5604 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28superio/winbond/w83627ehg: Convert romstage to generic componentEdward O'Callaghan
Convert the serial init to the generic romstage component and corresponding boards using this sio. Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5589 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28superio/winbond/w83627dhg: Convert romstage to generic componentEdward O'Callaghan
Convert the serial init to the generic romstage component and corresponding boards using this sio. Change-Id: I36bcf38c4351130be1ed924ecfe606336d0433f3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5588 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28superio/winbond/*: Provide common romstage componentEdward O'Callaghan
Following the reasoning of: cf7b498 superio/fintek/*: Factor out generic romstage component Change-Id: I3e889c0305c012e7556a5dd348e7f1e1ba629a9d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5587 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-06superio/winbond/w83627thg: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I1f7c20ac7841874125b6bfcd9f9db25d96355881 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5449 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-06superio/winbond/w83627ehg: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ib3a12fb8160729008bdaa8026365675a11325da0 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5448 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-13Eliminate some ASL warningsOskar Enoksson
The ASL compiler warned about "Control Method should be made Serialized (due to creation of named objects within)". This commit eliminates the warnings by changing those NonSerialized into Serialized. Change-Id: I639e769cf7a9428c34268e0c555a30c7dee1e04c Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/5189 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-12winbond/w83627hf/acpi: Fix some ASL warningsOskar Enoksson
There were ASL compiler warnings about "Size mismatch". This commit eliminates the warnings by changing the ASL declarations of those fields. Change-Id: If851ed4892ef6c96acbff861abd7001ab67d9d66 Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/5190 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-06uart8250: Drop includes in superioKyösti Mälkki
Change-Id: If723896cc31da75dbb3a63d5dc959764e96fded1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5139 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-03superio: Uncomment the w83627uhg UART clock source initializationDave Frodin
The asrock/imb-a180 mainboard is the first mainboard to use this w83627uhg/nct6627UD sio. The default h/w clock setting is 0. Adding the SIO in the mainboard Kconfig made the builder complain that the set_uart_clock_source() wasn't being used. So the calls to that function were uncommented. Change-Id: Iedba035237c5c0fa230b02ff4799bb8c1b7bbd4a Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/4573 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-08-15w83627hf/acpi: Move floppy drive enumeration from _INI into _FDE.Christoph Grenz
Move the floppy drive enumeration from _INI() and PROB(), which stored the enumeration results into _FDE into _FDE(). _INI is called by any ACPI-capable OS on boot while _FDE is rarely used. So it's better to run the enumeration when requested rather than unconditionally. Change-Id: Icf1e2a551806592faa8ba8d80fa8d02681602007 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/3604 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15w83627hf/acpi: Make `AddressMax` a multiple of `AddressAlignment`Christoph Grenz
The parallel port of the W83627HF can be configured on any port between 0x100 and 0xFFC with 4 byte alignment for traditional modes and 8 byte alignment for EPP mode. As the ACPI specification says that the maximum acceptable starting address has to be a multiple of the alignment granularity, correct the maximum starting address from 0xFFC to 0xFF8. Change-Id: I272e09d091149791f2867b1d06e4fc27bc1bb2cd Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/2942 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-15w83627hf/acpi: Fix logical device power down in ACPIChristoph Grenz
As Nico noticed for the W83627DHG, the power management bits to power down individual logical devices on Winbond superios are named counterintuitively and need to be set when the logical device should be powered. This corrects the power management methods for the W83627HF. Change-Id: I98bccd550a0513c62bfa9480275f88c566691bc8 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/3605 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-10w83627hf/acpi: Fix endianess error in floppy drive enumeration codeChristoph Grenz
The enumeration results are stored as five DWORDs in one 20 byte buffer. Bytes 3, 7, 11 and 15 were used to set the lowest bit of each DWORD. ACPI uses little endian, so 1, 4, 8 and 12 are the correct indices. Change-Id: I793225cb1bb62fd148ecfa1e61e02f5d7be62cdb Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/3602 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-04w83627hf/acpi: Fix offset of logical device activationNico Huber
The PnP's logical device activation normally resides at 0x30. This might have been overlooked as 0x29 looks very close to 0x30 in human eyes. Change-Id: Id5d5a92f2683ebe1808b943f686c062151d216da Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3592 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-04w83627hf/acpi: Fix type error in floppy drive enumeration codeChristoph Grenz
The enumeration method tried to evaluate an one-byte OperationRegion instead of a field in this OperationRegion, which resulted in an AE_TYPE error at runtime. Indexing the OperationRegion with a single field fixes this error. Change-Id: I15dd7aa6ecafb3a215d165d2b721003446815025 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/3603 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-03winbond/w83627dhg: Fix logical device power down in ACPINico Huber
The W83627DHG has some power managements bits to power down individual logical devices. These are called `* Power Down`. Counterintuitively and in contrast to `Immediate Power Down` (bit to power down the whole chip), these bits are set when the respective logical device is powered. Unfortunately, our ACPI code set them wrong which led to disabled devices after a S3 suspend/resume. Adding an option how to set the PM bits and setting them to zero for the W83627DHG, corrects it. Tested with kontron/ktqm77. Change-Id: I8a472d480d4277721bd17c9f7c2ce44fa84e8ae2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3590 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-03pnp: Add some default functions to enter/exit config stateNico Huber
Implement some common default functions to enter and exit the configuration state. Also provide default pnp_mode_ops for common enter()/exit() function pairs. The following cocci ensures their use: @ mode_match @ identifier enter, exit, ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = enter, .exit_conf_mode = exit, }; @ enter_match_8787 @ identifier mode_match.enter, dev; @@ enter(...) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } @ depends on enter_match_8787 @ identifier mode_match.enter, mode_match.ops; @@ struct pnp_mode_ops ops = { - .enter_conf_mode = enter, + .enter_conf_mode = pnp_enter_conf_mode_8787, }; @ enter_match_55 @ identifier mode_match.enter, dev; @@ enter(...) { outb(0x55, dev->path.pnp.port); } @ depends on enter_match_55 @ identifier mode_match.enter, mode_match.ops; @@ struct pnp_mode_ops ops = { - .enter_conf_mode = enter, + .enter_conf_mode = pnp_enter_conf_mode_55, }; @ depends on enter_match_8787 || enter_match_55 @ identifier mode_match.enter; @@ -enter(...) {...} @ exit_match_aa @ identifier mode_match.exit, dev; @@ exit(...) { outb(0xaa, dev->path.pnp.port); } @ depends on exit_match_aa @ identifier mode_match.exit, mode_match.ops; @@ struct pnp_mode_ops ops = { - .exit_conf_mode = exit, + .exit_conf_mode = pnp_exit_conf_mode_aa, }; @ depends on exit_match_aa @ identifier mode_match.exit; @@ -exit(...) {...} @ depends on enter_match_8787 || enter_match_55 || exit_match_aa @ @@ #include <device/pnp.h> +#include <superio/conf_mode.h> @ mode_match_55_aa @ identifier ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = pnp_enter_conf_mode_55, .exit_conf_mode = pnp_exit_conf_mode_aa, }; @@ identifier mode_match_55_aa.ops; @@ -struct pnp_mode_ops ops = {...}; @@ identifier mode_match_55_aa.ops, devops; @@ struct device_operations devops = { - .ops_pnp_mode = &ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; @ mode_match_8787_aa @ identifier ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = pnp_enter_conf_mode_8787, .exit_conf_mode = pnp_exit_conf_mode_aa, }; @@ identifier mode_match_8787_aa.ops; @@ -struct pnp_mode_ops ops = {...}; @@ identifier mode_match_8787_aa.ops, devops; @@ struct device_operations devops = { - .ops_pnp_mode = &ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; Change-Id: I1480336b54523cc95210d99cf31c1a0b3a14b464 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3484 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-07-01w83627hf: Add comments about parallel port modes in superio.aslChristoph Grenz
Add comments in PAR0._PRS explaining which dependent resource descriptor puts the parallel port into EPP or SPP mode. Change-Id: If4e224dbaf6f9105cde88d995d2e7c74fbf14502 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/3495 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-06-18winbond/w83627dhg: Correct resource setting for SPI (LDN6)Nico Huber
The SPI logical device on the W83627DHG uses the second i/o port register pair but not the first one. So we have to also set `io1` (the second io_info struct) and not `io0` in the pnp_info structure. Setting the PNP_IO1 flag without a mask in `io1` caused coreboot to hang in pnp_enable_devices() until commit aeead274 which added a check for an unset mask. Change-Id: I027d279b4641fecd88afb14d40fbe1c0bfbf81bb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3391 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-17pnp: Remove now plain wrappers for default PnP functionsNico Huber
After removing the enter()/exit() functions for configuration mode, most wrappers for our standard PnP functions just call the underlying default implementation. Remove those with a little cocci: @ op_match @ identifier op; identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$"; type device_t; identifier dev; @@ static void op(device_t dev) { pnp_op(dev); } @@ identifier op_match.op; @@ -op(...) {...} /* Three rules to match the alignment, hmmp... */ @@ identifier op_match.op, op_match.pnp_op; identifier ops; @@ struct device_operations ops = { - .set_resources = op, + .set_resources = pnp_op, }; @@ identifier op_match.op, op_match.pnp_op; identifier ops; @@ struct device_operations ops = { - .enable_resources = op, + .enable_resources = pnp_op, }; @@ identifier op_match.op, op_match.pnp_op; identifier ops; @@ struct device_operations ops = { - .enable = op, + .enable = pnp_op, }; Change-Id: Idc0e52c7e3600a01f3b6a4e17763557b271b481e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3483 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17pnp: Register implementations of enter/exit config stateNico Huber
Find all the (ramstage) implementations of enter()/exit() functions for the configuration state, register and call them through the new struct pnp_mode_ops. As our standard PnP functions are aware of the pnp_mode_ops, it's not necessary to call enter()/exit() around them anymore. Patch generated with the cocci below. It's not perfect. The movement of the enter()/exit() calls is somehow fragile. So I checked the remaining calls for sense, and changed some empty lines. Also a duplicate insertion of pnp_conf_mode_ops had to be removed. /* Try to find enter and exit functions by their outb() structure and their usage around calls to our standard pnp functions: */ @ enter_match @ identifier enter; identifier dev; type device_t; @@ void enter(device_t dev) { <... outb(..., dev->path.pnp.port); ...> } @ exit_match @ identifier exit; identifier dev; type device_t; @@ void exit(device_t dev) { <... outb(..., dev->path.pnp.port); ...> } @ pnp_match @ identifier op; identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$"; identifier enter_match.enter, exit_match.exit; type device_t; identifier dev; @@ void op(device_t dev) { ... enter(dev); ... pnp_op(dev); ... exit(dev); ... } /* Now add enter/exit to a pnp_mode_ops structure: */ @ depends on pnp_match @ identifier enter_match.enter; identifier exit_match.exit; identifier ops; @@ +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = enter, + .exit_conf_mode = exit, +}; + struct device_operations ops = { ..., + .ops_pnp_mode = &pnp_conf_mode_ops, }; /* Match against the new structure as we change the code and the above matches might not work anymore: */ @ mode_match @ identifier enter, exit, ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = enter, .exit_conf_mode = exit, }; /* Replace enter()/enter() calls with new standard calls (e.g. pnp_enter_conf_mode()): */ @@ identifier mode_match.enter; expression e; @@ -enter(e) +pnp_enter_conf_mode(e) @@ identifier mode_match.exit; expression e; @@ -exit(e) +pnp_exit_conf_mode(e) /* If there are calls to standard PnP functions, (re)move the enter()/exit() calls around them: */ @@ identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$"; expression e; @@ -pnp_enter_conf_mode(e); pnp_op(e); +pnp_enter_conf_mode(e); ... pnp_exit_conf_mode(e); @@ identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$"; expression e; @@ pnp_enter_conf_mode(e); ... +pnp_exit_conf_mode(e); pnp_op(e); -pnp_exit_conf_mode(e); @@ expression e; @@ -pnp_enter_conf_mode(e); -pnp_exit_conf_mode(e); Change-Id: I5c04b0c6a8f01a30bc25fe195797c02e75b6c276 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3482 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17pnp: Provide alternative pnp_enable() implementationNico Huber
The current default implementation of pnp_enable() only disables devices - if set so in the devicetree - but does not enable them. Enablement takes place in pnp_enable_resources(). Yet, many PnP chips implement their own version of pnp_enable() which also enables devices if set in the devicetree. It's arguable, if enabling those devices makes sense, before they get resources assigned. Maybe we can't write the resource registers if not, who knows? The least we can do is providing a common implementation for this behavior, and get rid of some code duplication. Used the following cocci: @@ expression e; @@ +pnp_alt_enable(e); -pnp_set_logical_device(e); ( -pnp_set_enable(e, !!e->enabled); | -(e->enabled) ? pnp_set_enable(e, 1) : pnp_set_enable(e, 0); | -if (e->enabled) { pnp_set_enable(e, 1); } -else { pnp_set_enable(e, 0); } ) Change-Id: I8d695e8fcd3cf8b847b1aa99326b51a554700bc4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3480 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17pnp: Unify some alignment to ease autogenerating patchesNico Huber
Most PnP drivers align the initialization of their `device_operations` with spaces. Unify this, so next autogenerated patches always match the alignment. Change-Id: I3f6baef6c8bb294c136354754125ea88c07a61a1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3479 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-11winbond/w83627dhg: Add ACPI supportNico Huber
This is loosely based on Christoph Grenz' ACPI code for the W83627HF and makes use of the PnP super i/o ACPI framework. Change-Id: I5e1cd09b83c0041f440562d2a1b73e4560589cb7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3288 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-10Drop prototype guarding for romccStefan Reinauer
Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1] made romcc not choke on function prototypes anymore. This allows us to get rid of a lot of ifdefs guarding __ROMCC__ . [1] http://review.coreboot.org/2424 Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3216 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-01Winbond W83627HF: Rename and move ASL snippet to `acpi/superio.asl`Paul Menzel
Put the ASL snippet for inclusion in the DSDT under the `acpi/` folder as it is done for the other Super I/O devices. $ find src/superio/ -name *asl src/superio/ite/it8772f/acpi/superio.asl src/superio/smsc/mec1308/acpi/superio.asl src/superio/smsc/sio1007/acpi/superio.asl src/superio/winbond/w83627hf/devtree.asl As there are no users of this file yet, no other adaptations need to be made. Change-Id: Id10cd8897592b780c9fd3bd6b45ada4cf1fcf33e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2937 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-15Super I/O W83627DHG: Enable UART B by redirecting pinsWolfgang Kamp
Pins 78-85 are set to GPIO after power on or reset. To enable UART B the pins must be redirected to it. Look at W83627DHG databook version 1.4 page 185 Chip (global) Control Register CR2C. Change-Id: I12b094a60d9c5cb2447a553be4679a4605e19845 Signed-off-by: Wolfgang Kamp <wmkamp@datakamp.de> Reviewed-on: http://review.coreboot.org/2626 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-28Remove assembly coded log2 functionRonald G. Minnich
As we move to supporting other systems we need to get rid of assembly where we can. The log2 function in src/lib is identical to the assembly one (tested for all 32-bit signed integers :-) and takes about 10 ns to run as opposed to 5ns for the non-portable assembly version. While speed is good, I think we can spare the 15 ns or so we add to boot time by using the C version only. Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1928 Tested-by: build bot (Jenkins)
2012-09-07superio winbond w83627dhg: add a function which is used on tyan s8226Siyuan Wang
this function is used on serial output of tyan s8226 Change-Id: I5f7fa535b922b224e381886f1bea64623fa549ef Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1494 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-22Auto-declare chip_operationsKyösti Mälkki
The name is derived directly from the device path. Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-02-16SIO: Winbond w83627dhg updateKerry Sheh
1. Stop include c file. 2. W83627dhg Pin 89, Pin 90 are multi function pins, add support to select them to I2C function. Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/565 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-01-11W83627HF: remove unused functionSven Schnelle
When CONFIG_EXPERT is set, compilation fails with: src/superio/winbond/w83627hf/superio.c:61:13: error: ‘w83627hf_16_bit_addr_qual’ defined but not used [-Werror=unused-function] cc1: all warnings being treated as errors This function isn't used in the code, so just remove it. Change-Id: I117e221fb3c3a20a7d7e7e2e86d7dbfdffc2cbff Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/533 Tested-by: build bot (Jenkins)
2011-11-22implement hwmon fan divisor setting for w83697hfFlorian Zumbiehl
Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/384 Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Tested-by: build bot (Jenkins)
2011-11-08make w83697hf_set_clksel_48() non-static and add a prototypeFlorian Zumbiehl
make w83697hf_set_clksel_48() non-static and add a prototype so as to get rid of warnings about it being unused Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/380 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 11:05:26 +0000