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2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-24superio: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I41191f6971bdd8ecff2c56f4bfa2b57c87530b83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80076 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-12-05superio/aspeed/ast2400/chip.h: Include <stdbool.h>Elyes Haouas
Change-Id: Ib4a0d77e7bb4cb52e91a5965cae0a6c7ddc40090 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70254 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-21src/superio: Remove unnecessary space after castsElyes Haouas
Change-Id: Iab76316f345fb0cf2ca2a3eaf40f64a1f1b7fc13 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69814 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14src/superio: Remove unused <device/pnp_def.h>Elyes HAOUAS
Change-Id: I835e8786b84ec16889fd08f566328bc7a0a60c90 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-08-18src: Remove unused 'include <delay.h>'Elyes HAOUAS
Change-Id: I6afea5c102299e570378a1656d3dcd329a373399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44093 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-29superio/aspeed/common: Add early configure functionsBryantOu
Add LPC read/write functions for access aspeed's memory, also create config data table to config memory and SIO. These functions are used at early stages to configure devices. Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com> Change-Id: Ib59c29a042b2c7bf196b8a5bd5218704d8075855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40483 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-25superio/aspeed/ast2400: drop non-onetime-config registers for iLPC2AHBMichael Niewöhner
The specified PNP registers PNP_MSC0-E (F0-FE) are part of the iLPC2AHB bridge's index/value interface. They are no one-time config registers so we can't specify a sane value in the devicetree. Thus, drop them to stop coreboot from complaining about the missing entries. Change-Id: I7d7f16845c755592317f140cca66cca12032f7a6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-25superio/aspeed/ast2400: rename SWAK to SWC to match the datasheetMichael Niewöhner
The datasheet uses "SWC" as shortcut for "System Wake-up Controller", thus rename it in the code. Change-Id: I8b3a14946e37f805d1c4e3df343dfcd7f67f6dc8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-30src/superio: replace license boilerplate with SPDXFelix Held
The authors from the header of the files are added in a previous commit. Change-Id: Iafeaafb9689c65bd2f5de3960097ec0d4c1009e7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38544 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-26superio/aspeed/ast2400: Fix Register OffsetChristian Walter
According to the specification the register offset must be 0x71 instead of 0x70. Change-Id: Icf69ffc701a42a31a4545ce53c13e2c2554863e1 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-17superio/aspeed/ast2400: Add AST2500 supportPatrick Rudolph
The AST2500 is similar to the AST2400, but it also supports ESPI mode. In ESPI mode the IRQ level must be 0 and UART3/UART4 aren't usable. Change-Id: Iea45740427ad56656040e6342f5316ec9d38122f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-05superio/{aspeed,nuvoton}: Fix typoElyes HAOUAS
Change-Id: I7772fadc756ceeef5988e4b1ecf8f93ad3605a84 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-02superio/aspeed: Remove unused aspeed include pathMartin Roth
Working on some other code, I noticed that superio/aspeed was added as an include path even though I wasn't using it. I investigated and found that NOTHING is using it. The files in the aspeed directory all reference files in their own directory. The supermicro x11-lga1151-series boards are the only ones using this SIO. TEST=util/abuild/abuild -t supermicro/x11-lga1151-series Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I377066451a50452c17c9bfaa0f815f69e039984e Reviewed-on: https://review.coreboot.org/c/coreboot/+/37390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04superio/aspeed/common: add workaround for serial routing delay quirkMichael Niewöhner
Some mainboards with an ASPEED BMC do the serial routing setup in the BMC boot phase on cold boot. This results in scrambled console output when this is not finished fast enough. This adds a delay of 500ms as workaround in the BMCs uart setup that can be selected at mainboard level. A user may disable the workaround when using another BMC firmware like OpenBMC, u-bmc or some custom BMC bootloader with fast serial setup. Change-Id: I7d6599b76384fc94a00a9cfc1794ebfe34863ff9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36591 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20src: Remove unused 'include <string.h>'Elyes HAOUAS
Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-16src/superio: Remove unused 'include <console/console.h>'Elyes HAOUAS
Change-Id: Iaeb69c5e7cb3345f4f2ff90eef4f97d72c722ca2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-16src/superio: Remove unused 'include <arch/io.h>'Elyes HAOUAS
Change-Id: Ia08e27da51f1f523232379960dc21c1ba4849932 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-06src/superio/aspeed/ast2400: Use new SuperIO acpigenChristian Walter
Use the new SuperIO ACPI generator to make includes in DSDT obsolete. Manually tested on X11SSH-TF and verified that ACPI tables are correct. Change-Id: I2ef49bb6f733994b249ae46f0460234380b552b8 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33253 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-24superio: Add ASpeed AST2400Frans Hendriks
Add support for ASpeed AST2400. This device uses write twice 0xA5 to enter config mode. BUG = N/A TEST = ASRock D1521D4U Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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