coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-01-26	superio/aspeed/ast2400: Fix Register Offset	Christian Walter
	According to the specification the register offset must be 0x71 instead of 0x70. Change-Id: Icf69ffc701a42a31a4545ce53c13e2c2554863e1 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-17	superio/aspeed/ast2400: Add AST2500 support	Patrick Rudolph
	The AST2500 is similar to the AST2400, but it also supports ESPI mode. In ESPI mode the IRQ level must be 0 and UART3/UART4 aren't usable. Change-Id: Iea45740427ad56656040e6342f5316ec9d38122f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-05	superio/{aspeed,nuvoton}: Fix typo	Elyes HAOUAS
	Change-Id: I7772fadc756ceeef5988e4b1ecf8f93ad3605a84 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-20	src: Remove unused 'include <string.h>'	Elyes HAOUAS
	Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-16	src/superio: Remove unused 'include <console/console.h>'	Elyes HAOUAS
	Change-Id: Iaeb69c5e7cb3345f4f2ff90eef4f97d72c722ca2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-16	src/superio: Remove unused 'include <arch/io.h>'	Elyes HAOUAS
	Change-Id: Ia08e27da51f1f523232379960dc21c1ba4849932 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-06	src/superio/aspeed/ast2400: Use new SuperIO acpigen	Christian Walter
	Use the new SuperIO ACPI generator to make includes in DSDT obsolete. Manually tested on X11SSH-TF and verified that ACPI tables are correct. Change-Id: I2ef49bb6f733994b249ae46f0460234380b552b8 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33253 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-24	superio: Add ASpeed AST2400	Frans Hendriks
	Add support for ASpeed AST2400. This device uses write twice 0xA5 to enter config mode. BUG = N/A TEST = ASRock D1521D4U Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>