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Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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De-asserts STRAP_BIF_all_valid for
PCIE-GFX core.
After lane reversal,
Asserts STRAP_BIF_all_valid for
PCIE-GFX core.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: QingPei Wang <wangqingpei@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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> Stefan Reinauer wrote:
> > The specified IO port is most likely wrong. As the comment mentions, the
> > SSDT is a good place for that. A preprocessor define used both in the
> > CPU init code and in the asl would solve the problem without an SSDT.
> > For some info on CPU SSDT creation on intel check out
> > src/cpu/intel/speedstep/acpi.c
>
> The IO port is ok (and I wrote the comment myself ;)):
> DEFAULT_PMBASE is 0xe400
> PCNTRL reg offset is 0x10
>
> Using the preprocessor will probably work too if iasl can do simple
> arithmetic (likely yes), I'll look into that.
BTW, my first idea was to use an acpi method that looks up pmbase in
the pci cfg space, but when I define a method like this:
Method(TEST, 2)
{
Return (Add(Arg0, Arg1))
}
I get:
|build/mainboard/asus/p2b/dsdt.ramstage.asl 9: Processor (CPU0,
|0x01, TEST(0xe400, 0x10), 0x06) {}
|Error 4096 - syntax error, unexpected PARSEOP_NAMESEG,
|expecting ')' ^
While using the builtin Add() directly works.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6130 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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I cleaned up the patch and moved most of the dsdt.dsl and
acpi_tables.c into the southbrige/northbridge directory.
Updated patch should fix abuild error and incorporates suggestions
on irc by uwe (thanks for the comments).
Thanks to Idwer Vollering <vidwer@gmail.com> for the original patch.
Tested:
Linux (poweroff, powerbutton event)
XP (poweroff, powerbutton event)
Abuild-tested
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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In bcm5785_enable_rom(): Use PCI IDs from pci_ids.h instead of hardcoding,
and use 'dev' instead of 'addr' as device_t variable name.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6125 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Also, add missing license header to amd8111_enable_rom.c, add some more code
comments and use PCI IDs from pci_ids.h instead of hardcoding.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Also, move CONFIG_HT_CHAIN_END_UNITID_BASE #ifdef block to mcp55.h to make
the build work (but this is a good idea anyway, as it's used in
multiple files).
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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initialized properly because the pcie link takes some time to come
up.
I set the timeout rather arbitrary to 100ms, this is what a BIOS_ERR
and higher only boot looks like on my system (with pcie printks set
to BIOS_ERR so they show up):
|Device error
|Device error
|PCI: 00:02.0 PCIe link up after 35800 us
|PCI: 00:03.0 PCIe link up after 12900 us
|PCI: 00:03.1 PCIe link timeout
|PCI: 00:03.2 PCIe link up after 32000 us
|APIC: 00 missing read_resources
|I2C: 01:50 missing read_resources
|I2C: 01:51 missing read_resources
|I2C: 01:52 missing read_resources
|I2C: 01:53 missing read_resources
|Start bios (version pre-0.6.2-20101025_023503-nukunuku)
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6121 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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AMD RS780 uma graphics. Tested with frame buffer sizes 64m through 1GB
by running dxdiag and Windows media player at 1600x1200 true color.
Additional changes needed to boot Win7 on Mahogany_fam10 will follow.
-- Enable and program the debug bar as required by the ATI graphics driver.
First, make the debug bar writable and allow resource allocation code
to program it. Once programmed, enable its operation.
-- Disable the family 10h processor mmconf while the RS780 mmconf is in use.
-- Make strap programming more closely follow the reference BIOS.
-- Disable PCIe bar 3 after using it.
-- UMA size is no longer hardcoded.
-- Disable write combining for all steppings to eliminate stability problem.
-- Correct task file data.
-- Improve the accuracy of the Atom table that passes information to the driver.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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CONFIG_HAVE_ACPI_RESUME == 1 getting rid of ugly define in romstage.c
2) the patch implements get_cbmem_toc in chipset specific way if defined.
On Intel targets it should be unchanged. On K8T890 the the cbmem_toc is read from NVRAM. Why you ask? Because we cannot do it as on intel, because the framebuffer might be there making it hard to look for it in memory (and remember we need it so early that everying is uncached)
3) The patch removes hardcoded limits for suspend/resume save area (it was 1MB) on intel. Now it computes right numbers itself.
4) it impelements saving the memory during CAR to reserved range in sane way. First the sysinfo area (CAR data) is copied, then the rest after car is disabled (cached copy is used). I changed bit also the the copy of CAR area is now done uncached for target which I feel is more right.
I think I did not change the Intel suspend/resume behaviour but best would be if someone can test it. Please note this patch was unfinished on my drive since ages and it would be very nice to get it in to prevent bit rotten it again.
Now I feel it is done good way and should not break anything. I did a test with abuild and it seems fine.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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initializing VGA happens pretty much as the last thing before starting the
payload. Hence, drop VGA console support, as we did in coreboot v3.
- Drop VGA and BTEXT console support.
Console is meant to be debugging only, and by the time graphics comes up
99% of the risky stuff has already happened. Note: This patch does not remove
hardware init but only the actual output functionality.
The ragexl driver needs some extra love, but that's for another day
- factor out die() and post()
- drop some leftover RAMBASE < 0x100000 checks.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: QingPei Wang<wangqingpei@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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default on all boards) into Kconfig.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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not brought over to Kconfig (this applies to all #defines to 4, as
that's the default anyway)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do.
- spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of
romstage.c files and lots of spd_addr.h files. Don't even bother for
those spd_addr.h which aren't even actually used, drop them right away.
- Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1,
and 0xa0 with (DIMM0 << 1) where appropriate.
- Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0,
SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC.
- VIA VX800: Drop unused SMBUS_ADDR_CH* #defines.
- VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do.
Then, replace 0xa0 (which now becomes 0x50) with DIMM0.
- alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes.
- Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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addressing scheme to match the rest of the tree
(0x50 instead of 0xa0).
abuild tested.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- s/Options.lb/devicetree.cb/
- s/Config.lb/devicetree.cb/
- s/cache_as_ram_auto.c/romstage.c/
- h8dmr_fam10/README: Drop obsolete comment, we have mc_patch_01000086.h in
the tree now.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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chipset code (where it belongs)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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as an ACPI motherboard resource or it will not enable MMCONFIG
and the extended pcie configuration area will be unaccessible:
This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF
resource flags to do this.
I also added a new resource for the mapped bios rom area just below 4GB.
I'm not sure if the choice for the index parameter of new_resource()
is correct though.
Note that the bios rom decode is enabled in
src/southbridge/via/vt8237r/vt8237r_early_smbus.c
for the whole 4MB area (even though the comment says 1MB).
Ruik: I extended the flash range to 16MB (This is what VT8237S can decode)
Remove the MMCONFIG region reserve in the mainboard file (this patch makes it obsolete)
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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CONFIG_PIRQ_ROUTE) so far is the amd cs5530.
Add one for vt8237 too.
Setting up the pci routing is important in case you want to boot DOS,
OSes that don't support ACPI or MP tables and ROMs for add-in storage
controllers may depend on this too.
TODO: Fix the 4 routing links limitation in
src/arch/i386/boot/pirq_routing.c
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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For now this is a plain copy of the ASUS A8V-E SE target, I reported
that most of the code also works (sort of) for the ASUS A8V-E Deluxe
a long while ago, see
http://www.coreboot.org/pipermail/coreboot/2008-March/031866.html
http://www.coreboot.org/ASUS_A8V-E_Deluxe
There will be a bunch of changes necessary though (devicetree.cb, mptable.c,
ACPI, etc) which do not apply to the A8V-E SE, so we need an extra target.
Also: Increase ID_SECTION_OFFSET on the VIA K8T890/K8M890 southbridge, as
otherwise there will be build errors if the MAINBOARD_PART_NUMBER string
gets too long (as is the case for "A8V-E Deluxe"). The error is:
ld: section .id loaded at [00000000ffffffd2,00000000ffffffef] overlaps
section .romstrap loaded at [00000000ffffff80,00000000ffffffd3]
(both with stock Debian gcc and with xgcc)
Increase ID_SECTION_OFFSET (default 0x10) to 0x80 as other southbridges do.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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an override function in m2v/mainboard.c
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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cablesel |= (sb->ide0_80pin_cable << 28) |
(sb->ide0_80pin_cable << 20) |
(sb->ide1_80pin_cable << 12) |
(sb->ide1_80pin_cable << 4);
in vt8237r_ide.c ends up doing
cablesel |= 0xfffffff0;
(with both bits set to 1) which is probably not the intended result. ;)
After a short discussion on irc the consensus was to change the
bitfields to u8 as it's probably not worth it using bitfields here.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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I missed this one since it was working anyway, since
"The LPC BIOS ROM is always accessed when ISA addresses
FFF80000-FFFFFFFF and 000F0000-000FFFFF are decoded" (VT8237R datasheet)
And the rom I use for testing is smaller than this 512KB default range.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Needed to change class from raid to ide so seabios can boot from it.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This patch fixes a hang on
supermicro/h8dme
supermicro/h8dmr
supermicro/h8dmr_fam10
and possibly on other mcp55-based boards.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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"Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid()" patches.
This adds VT8237A specific VLINK/LPC init in vt8237r_early_smbus.c
I ran some tests and apparently both the
| /* So the chip knows we are on AMD. */
| pci_write_config8(devctl, 0x7c, 0x7f);
and
| /*
| * Allow SLP# signal to assert LDTSTOP_L.
| * Will work for C3 and for FID/VID change.
| */
| outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
in vt8237r_early_smbus.c are needed on VT8237A, otherwise I get a (non-fatal)
fid/vid change error on boot.
While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(),
vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init().
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Depends on the "Introduce get_vt8237_lpc() function" patch.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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I broke this out into a seperate part to keep the other half as
straight-forward as possible.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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add a get_vt8237_lpc() function.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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http://linux.via.com.tw/ as VX800 seems to be compatible.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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and vt8237r_lpc.c.
While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(),
vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init().
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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vt8237r_lpc.c
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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hang. Also need to set lane config to 0x00 for autonegotiation.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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variant. It also adds additional dev_find_device calls in k8t890_ctrl.c for
subfunctions 3 and 7.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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operation within is NULL anyway.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Add enable_intel_82093aa_ioapic() which enables IOAPIC usage in the
Intel 82371EB southbridge (sets the proper chip-select) and sets an
IOAPIC ID.
- We only call enable_intel_82093aa_ioapic() if a board does "select IOAPIC"
as on 82371EB-based boards the IOAPIC is an external chip (not integrated
in the southbridge) and it's only populated on multi-CPU boards.
That is, we cannot unconditionally enable it, only on SMP-capable boards.
- Due to the reason explained above, remove "select IOAPIC" from
src/southbridge/intel/i82371eb/Kconfig, and add it to
src/mainboard/asus/p2b-d/Kconfig.
- Also set CONFIG_MAX_PHYSICAL_CPUS to 2 on ASUS P2B-D. There are two
CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs
didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already).
- Drop useless/duplicated enable_lapic() call from ASUS P2B-D's romstage.c,
that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC
are set.
- Rework ASUS P2B-D mptable.c to fix a number of things:
- Convert it to use mptable_write_buses() as all mptable.c files should do.
- Fix incorrect IOAPICID (it's 0x11 for the external 82093AA IOAPIC).
- Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc.
This is build-tested on ASUS P2B-D, and also boot-tested successfully there.
On Linux I now get two entries in /proc/cpuinfo (where only one appeared
before this patch), i.e. both populated CPUs are found.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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boards using ck804_early_setup.c that select CK804_USE_NIC.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Additionally, make the second SMBus more accessible in romstage.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Also, make them all fit in 80chars/column, fix some whitespace issues
and also some typos I noticed.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Right now, it breaks the build of bootblock enabled boards
with that chipset.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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eliminates the compiler warning that causes the build to fail.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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BIOS related BSODs. Win7 checked build complains when running coreboot+seabios:
FADT revision inconsistent with length.
Revision: 0x1
Length: 0xf4
Expected Length: 0x74
Change the FADT revision from 1 to 3 to match its length and prevent the Windows checked build assert.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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#ifdef DEADCODE out smbus_write_byte() and smbus_write_block() as
they are static and nothing uses them or are incompletely implemented.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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It affects only systems booting from SPI flash, not those booting from
LPC flash. By default, the SB700 reads dwords from the SPI flash chip.
Setting PrefetchEnSPIFromHost causes the SB700 to read entire cache
lines from the flash chip.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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to zero, so for boards with RS780 not on CPU's HT chain 0, the function will
mis-configure the MMIO dst-link routing, and the following enable_pcie_bar3()
function will hang when it visits the MMIO.
The following patch fixes the problem, and is tested on a K8 board with RS780
on HT chain 1.
Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Fix that to read the register from the chain where the SB chip is on.
Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This is pretty much the same mechanism as in r5929.
- Use 'romstage-y' to turn i82801ax_early_smbus.c and i82801bx_early_smbus.c
into distinct compilation units, and don't #include the files anymore
in romstage.c files.
- Ditto for northbridge/intel/i82810/raminit.c, and
northbridge/intel/i82810/debug.c.
- Add various header files which are now needed, drop unused includes.
- Make functions that need to be visible non-static.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Some mainboards need to disable the power button to avoid turning off
right after being turned on, while other boards ship with a jumper over
the power button and should allow the user to configure the behavior.
This adds infrastructure in the form of four mutually exclusive options
which can be selected in a mainboard Kconfig (power button forced on/off,
and user-controllable with default on/off) and one result bool which
source code can test. (Enable the button or not.)
The options have been implemented in CS5536 code and for all mainboards
which select SOUTHBRIDGE_AMD_CS5536, but should be used also by other
chipsets where applicable. Note that if chipset code uses the result
bool ENABLE_POWER_BUTTON, then every board using that chipset must
select one out of the four control options in order to build.
All touched boards should have unchanged behavior, except
pcengines/alix1c, traverse/geos and lippert/hurricane-lx where the
power button can now be configured by the user.
Build tested for alix1c, alix2d, hurricane-lx and wyse-s50. Confirmed
to work as advertised on alix1c both with button enabled and disabled.
Includes additional traverse/geos changes from Nathan and
lippert/hurricane-lx changes from Jens to correctly use the new
feature on those boards.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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As both ioapic.h and acpi.h define a macro named "NMI", rename one
of them (NMI -> NMIType in acpi.h).
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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BTW, embed the always-the-same string instead of referencing it through "%s".
Do the same for i82371EB while we're at it.
Signed-off-by: Sylvain Hitier <sylvain.hitier@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5940 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Drop all non-ICH2 "struct pci_driver" entries from all files.
- Kconfig: Add missing USE_WATCHDOG_ON_BOOT.
- Drop i82801bx_sata.c and i82801bx_usb_ehci.c, ICH2 doesn't have SATA/EHCI.
- Simplify lots of code, getting rid of i82801xx remainders.
- Use u8 et al (instead of uint8_t) in a few more places.
- Use #defines from header files where possible.
- Various other fixes and updates.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5934 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Following patch enables UDMA on ALL IDE devices. The current code enables it only for primary master, which causes my DVD drive to fail under windows install
and even after hard reset in linux (DMA seems lockup).
The fix should not have any influence for Linux because the IDE driver will
correctly reprogram this bit.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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primary / secondary IDE channel with SATA (in IDE mode).
The bug was that setup was done in wrong device.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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only for primary master, which causes my DVD drive to fail under windows install
and even after hard reset in linux (DMA seems lockup).
The fix should not have any influence for Linux because the IDE driver will
correctly reprogram this bit.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Use 'romstage-y' to turn i82371eb_early_pm.c and i82371eb_early_smbus.c
into distinct compilation units, and don't #include the files anymore
in romstage.c files.
- Ditto for lib/debug.c, northbridge/intel/i440bx/raminit.c, and
northbridge/intel/i440bx/debug.c.
- Add various header files which are now needed.
- Make functions that need to be visible non-static.
- Drop a remaining "select ROMCC" from a 4440BX board.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Idwer Vollering <vidwer@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Nothing ever calls the functions in these files, and we already have
i82801ax_watchdog.c and i82801bx_watchdog.c which basically do the same
_and_ are hooked up correctly in the Makefile.inc and via the
USE_WATCHDOG_ON_BOOT mechanism.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Remove left-overs from more generic code in i82801xx times, and fix
register names as needed.
- Simplify IDE init code (and save some ROM space too).
- Simplify PIRQ code.
- Use u8 et al instead of uint8_t everywhere.
- Random other fixes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Fix incorrect #includes, add missing ones.
- Drop unused do_smbus_write_block() and smbus_wait_until_blk_done().
- Pass smbus_io_base to all functions as the other ICH implementations do.
- Random other fixes which are required to make it build.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5924 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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bit in the AMD processor 'MMIO Limit Address Register'.
I suspect it is because of a typo where 0x80 was entered
as 0x8. If 0x80 is used, then the strap configuration
register accesses become non-posted, which is how the
Shiner reference BIOS does it.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Also:
Unfortunately Intel 440BX + 82371AB/EB/MB boards can have their ISA device
on various PCI bus:device.function locations.
Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.
Thus, instead of hardcoding PCI bus:device.function numbers such as
PCI_DEV(0, 7, 0), we now simply find the ISA device via PCI IDs, which
works the same on all boards.
As an additional benefit this patch also gets rid of one .c file include
in romstage.c.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig.
- Add the following in src/cpu/intel/slot_1/Makefile.inc:
cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
- Remove "select ROMCC" from all 440BX board Kconfig files.
- Drop all early_mtrr_init() calls, that's done by CAR code now.
Various small fixes were needed to make it build:
- Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(),
those were never called anyways.
- Remove the "static" from the main() functions in romstage.c files.
- Always call dump_spd_registers() from the 440BX debug.c, but use
"#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging
is enabled in menuconfig.
- Drop all "lib/ramtest.c" #includes and ram_check() calls (even if
commented out) from romstage.c's, as we've done for most other boards.
- Add missing #includes or prototypes. Some of the prototypes will be
removed later when we get rid of the #include'd .c files.
Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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CK804_USE_NIC, CK804_USE_ACI, CK804_NUM.
MCP55_USE_NIC, MCP55_USE_ACI, MCP55_NUM.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Pter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges
- drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Remove many more .c-includes from i945 based boards.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The AMD SB700 allows changing the physical USB port to be used as
USB Debug Port, implement support for this.
Also, fix incorrect PCI device of the SB700 EHCI device. Actually, the
SB700 has _two_ EHCI devices (D18:F2 and D19:F2), but for now we only use
D18:F2. Our generic USBDEBUG code cannot handle multiple EHCI PCI devices
currently, AFAICS.
Hook up all SB700 boards to the CONFIG_USBDEBUG_DEFAULT_PORT facility.
Untested, but should work.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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at the same time let the user specify sources instead
of object files:
- objs becomes ramstage-srcs
- initobjs becomes romstage-srcs
- driver becomes driver-srcs
- smmobj becomes smm-srcs
The user servicable parts are named accordingly:
ramstage-y, romstage-y, driver-y, smm-y
Also, the object file names are properly renamed now, using
.ramstage.o, .romstage.o, .driver.o, .smm.o suffixes consistently.
Remove stubbed out via/epia-m700 dsdt/ssdt files - they didn't
easily fit in the build system and aren't useful anyway.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coreystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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We don't surround the <usbdebug.h> #include with those checks in other
places either. Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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that component rather than the mainboard.
The intel/d810e2cb is the only board using the i82801bx southbridge.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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is selected that uses a chipset which actually has that functionality _and_
we have code to initialize the Debug Port in coreboot (for that chipset).
Also, remove the duplicate list of PCI IDs and just link to the wiki page at:
http://www.coreboot.org/EHCI_Debug_Port
The list is now less useful in the kconfig help as this option will only
appear for those boards where it's actually supported.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Use PCI_COMMAND and PCI_COMMAND_MEMORY from pci_def.h instead of
hardcoding their values.
- SB600/SB700: Drop useless/unused SB600_DEVN_BASE and SB700_DEVN_BASE.
- ICH7: Drop unused EHCI_CONFIG_FLAG and EHCI_PORTSC.
- s/uint32_t/u32/.
- Cosmetics, whitespace, coding style fixes and added code comments.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Drop unused DBGP_DEFAULT #defines on boards with chipsets where no
USB Debug Port support is implemented anyway (at the moment, at least):
- hp/dl145_g3
- hp/dl165_g6_fam10
- ICH7: Move unrelated code out of set_debug_port(). All ICH southbridges
with Debug Port hardcode the physical USB port used as Debug Port to 1.
In other words, this port is not user-configurable (as seems to be
the case on NVIDIA MCP55). For now we keep the 'port' parameter in order
to not change the API, this might be fixed differently later.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Also fixes random whitespace issues, typos, etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Without a (currently) dummy set_debug_port() function the build fails,
this may or may not be fixed differently in the future.
Manually build-tested on all SB600/SB700 boards, and tested on hardware on
one SB600 board I own, works fine.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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consits of weak function which always exists (with defaults) and a possibility to
override this with normal function in main.c. This is the other way of
doing that and not using the devictree.cb.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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After we splitted up the old i82801xx driver which was supposed to support
multiple generations of ICH* chipsets, some of the generified code
is now obsolete in i82801ax which should only cover ICH/ICH0 and none of
the later ICH* generations.
Hence:
- Drop "struct pci_driver" entries for chipsets other than ICH/ICH0.
- Drop drivers for hardware that is not present on ICH/ICH0: NIC, SATA, EHCI.
- Drop PIRQE-PIRQH #defines and code, not available on this chipset.
- Simplify some parts of the code (more will follow).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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On this board all reads from SPD return 0xff by default, there's a custom
GPIO fiddling needed to enable access to the SPD SMBus offsets at
0x50-0x53. While coreboot actually sort of booted sometimes before r5193,
that was just sheer luck as the RAM init was hardcoded in certain ways.
Since the proper, more heavily SPD-based RAM init the brokenness of the
ASUS P3B-F RAM init was becoming visible.
This patch uses GPIOs to enable access to the SPD SMBus offsets,
and resets the GPIOs again after RAM init (this is needed to allow for
lm-sensors to work, for example).
Tested successfully on hardware.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Idwer Vollering <vidwer@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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to make sure MMCONF is set up before use. Otherwise, PCI config
accesses run before init_cpus() will be lost if MMCONF is enabled
(unless explicitly done as port-based accesses).
This obsoletes removal of RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78) in
mcp55_early_setup, so reinsert.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Juhana Helovuo <juhe@iki.fi>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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fixes a few alignment wrinkles and sets up and registers the MMCONF area
for AMD Fam10h CPUs (where selected by mainboard configuration). It
removes a bit of code that proved troublesome in MMCONF setups from
mcp55_early_setup_car.c, as per earlier discussion.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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ready (PSON gating). Some boards boot faster than this power well
stabilization, and thus see bad data when accessing the smbus
registers.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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For boards where timer2 is unusable, there's still the IO based
initialization available using the Kconfig option TSC_CALIBRATE_WITH_IO
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Kevin O'Connor <kevin@koconnor.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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and SB600.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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chipset support it. But this involves a long list of 'depends', which you have
to remember updating manually. Converted this into HAVE_... properties, which
will be inherited automatically if someone copies a chipset to create a new
one.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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