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2019-08-12sb/intel/i82801dx: Drop unused parameterKyösti Mälkki
Change-Id: I4aaa67ba3de82b07e0e278be39a93a482bbf09c4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34819 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-28sb/intel/common/spi: Fix opmenu setupNico Huber
Remove a spurious reference: the `optype` field is already the pointer we want. Change-Id: I65eb3a519db9037c84750c5d40e3f19a1e360361 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-26sb/intel/bd82x6x: Add support to disable xHCIPatrick Rudolph
Set FD bit if xHCI is disabled in devicetree. Change-Id: I3d08ded10daea6d86857ebbbf3f8dcc85ebe9df4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-07-23include/spi-generic: Append unit to macro namesUwe Poeche
This patch appends a unit (milliseconds) to time-out macro names for better understanding the code which is using the macros. Change-Id: Ibc4beda2660a83fd5f0ed325b2ee3148c6d96639 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34384 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-23sb/intel/common/spi: Increase flash erase timeoutUwe Poeche
This patch provides an increased timeout (60ms -> 1s) for SPI HW-sequencing flash erase operations. Without that the erase for MRC cache writing on siemens/mc_bdx1 sometimes goes wrong because the timeout stops waiting for flash cycle completion. It was found during continuous integration. Investigation showed that the used flash type takes sporadic (e.g. 5% of the test cycles) more time for completion of erasing operation if the ambient temperature increases. The measured time values are in range of data sheet of SPI flash. 60ms is a typical value. So increasing the value is necessary. tested on siemens/bdx1; measured time values with increased ambient temperature of flash were always smaller than worst case value of 1s. Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-20mb/,sb/intel/i82801gx: Merge `ide_legacy_combined` into `sata_mode`Nico Huber
Functional changes were already done in 5eb81bed2e (sb/intel/i82801gx: Detect if the southbridge supports AHCI) but we forgot to update the `chip.h` and devicetrees. Change-Id: I0e25f54ead8f5bbc6041d31347038e800787b624 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34462 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supportedPatrick Rudolph
The processor P_BLK doesn't support throttling. This behaviour could be emulated with SMM, but instead just update the FADT to indicate no support for legacy I/O based throttling using P_CNT. We have _PTC defined in SSDT, which should be used in favour of P_CNT by ACPI aware OS, so this change has no effect on modern OS. Drop all occurences of p_cnt_throttling_supported and update autoport to not generate it any more. Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-19sb/amd/sb800: Remove bit shift that does nothingJacob Garber
This bit shift attempts to set bits 8 and 9 of the byte variable (counting from 0). However, as the name suggests, this variable is only 8 bits wide, so the shift does nothing. Reading section 7.5 of the AMD SB800-Series Southbridges Register Programming Requirements manual, bits 8 and 9 are already set by default, so we can remove the bit shift. (Alternatively, we could try setting the corresponding bits one byte higher in 0xF1 if needed.) Change-Id: I645236441e02925ee01339378d213cb343027363 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229582 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-19src: Make implicit fall throughs explicitJacob Garber
Implicit fall throughs are a perpetual source of bugs and Coverity Scan issues, so let's squash them once and for all. GCC can flag implicit fall throughs using the -Wimplicit-fallthrough warning, and this should ensure no more enter the code base. However, many fall throughs are intentional, and we can use the following comment style to have GCC suppress the warning. switch (x) { case 1: y += 1; /* fall through */ case 2: y += 2; /* fall through - but this time with an explanation */ default: y += 3; } This patch adds comments for all remaining intentional fall throughs, and tweaks some existing fall through comments to fit the syntax that GCC expects. Change-Id: I1d75637a434a955a58d166ad203e49620d7395ed Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-18sb/intel/bd82x6x: Add and use more RCBA definesPatrick Rudolph
Taken from "Intel 6 Series Chipset and Intel C200 Series Chipset" Document Number: 324645-006 and "Intel 5 Series Chipset and Intel 3400 Series Chipset" Document Number: 322169-004 and "Intel 6 Series Chipset" Document Number: 324645-001. UPDCR was found in GNU/Linux's drivers/pci/quirks.c. DMC2 was guessed as it's close to DMC and defined for 5 series chipset. Test: Run BUILD_TIMELESS=1 and compared the coreboot.roms, no differences. Change-Id: I4fed7c38078cabd4308424c7547416e87c9e6fa7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-17sb/amd/sr5650: Add fine-grained bounds checkingJacob Garber
The code currently checks that 4 <= dev_index <= 10, which after subtraction by 4 can index into an array of length at most 7. This is fine for the largest cpl array (which does have length 7), but is too large for some of the others, which are smaller. This adds bounds checks for each array access to ensure they are all within bounds. Change-Id: I1610d35ca6cbb6cfb42c251e75b0e8b22b64252b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229676 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-17intel/i82801ix: Refactor lock_smm()Kyösti Mälkki
Move the SMM lock outside the function as it is renamed. Replace conditional !PARALLEL_MP with SMM_ASEG to better reflect the use. Change-Id: I93bf0d2f711f94a5bb741bdcd92c1e0fec228684 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-17intel/i82801gx,i82801jx: Rename lock_smm()Kyösti Mälkki
With PARALLEL_MP the lock has been moved elsewhere. Change-Id: I2db78fe99aa1d46c5e7bcef99a37619301c98914 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-16sb/amd/{cimx,}/sb{700,800,900}: Prevent uninitialized readsJacob Garber
There are two hard things in computer science: cache invalidation, naming things, and off-by-one errors. -- Anonymous var_num records the number of initialized entries in the reg_var array. However, this means the index of the last initialized element is one less than the value of var_num, so we need to take that into account when indexing into the array. This has already been fixed in several other places (eg. sb/amd/pi/hudson/lpc.c), so let's also do so here. Change-Id: Ibefabaca42866a3f2b22eff979c73badf86ac317 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: scan-build 8.0.0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-13soc,southbridge/intel: Avoid preprocessor with HAVE_SMI_HANDLERKyösti Mälkki
Change-Id: Id375999adad71d95d4968398e90bc3c07f65ea83 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34254 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13intel/fsp_rangeley: Avoid preprocessor with HAVE_SMI_HANDLERKyösti Mälkki
Change-Id: Id9abc239a92fa7d3e29738f08f2ccdaf3232dfb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-13intel/e7505,i82801dx: Fix SMM_ASEG lockKyösti Mälkki
In our codebase, this is only coupled with intel/e7505. The PCI registers reference here were for intel/i945. Also aseg_smm_lock() was previously not called. Change-Id: I21d991c8c2f5c2dde1f148fd80963e39d9836d3c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34149 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12src: Add missing include <device/pci_ops.h>Elyes HAOUAS
Change-Id: Iae73fc1557fb310dacbbf8bc486dc3cc5249d9e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33526 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-10sb/nvidia/ck804: Remove old debugging codeJacob Garber
These printk() statements were added in commit cdc526e582 (southbridge/nvidia/ck804: Fix boot hang on ASUS KFSN4-DRE w/ K8 CPU) when debugging another issue. They have undefined reads if ck804_num is 0 and aren't needed anymore, so drop them. Change-Id: I80b775370ac6485958948f0bff4510755a6cd2b8 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 137058{1,3} Reviewed-on: https://review.coreboot.org/c/coreboot/+/33459 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-10intel/i82801ix: Rename smm_lock() prototypeKyösti Mälkki
This southbridge code may be built with either ASEG or TSEG. Fix minor collision in namespaces. Change-Id: I04f90fb308c280621a3037fee4bece1e5655480e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-09cpu/x86: Declare SMM_ASEGKyösti Mälkki
This is really an inverse of SMM_TSEG to flag platforms that should potentially move away from ASEG implementation. Change-Id: I3b9007c55c75a59a9e6acc0a0e701300f7d21f87 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-09arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08sb/intel/lynxpoint: Use common final SPI OPs setupArthur Heymans
Change-Id: I12e238b3a33c909103986822bd7398e1c3bac676 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-08sb/intel/ibexpeak: Use common final SPI OPs setupArthur Heymans
This also removes the relevant RCBA replays the mainboard dir. Change-Id: I75dd9d1bcd09d835f205a51c087d52ebb4e166f6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Thomas Heijligen <src@posteo.de>
2019-07-08sb/intel/i82801gx: Use common final SPI OPs setupArthur Heymans
Change-Id: I30f80c237bccf8dc350249fd12ca6c4559d23d4f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-08sb/intel/common: Add a common interface to set final OPs settingsArthur Heymans
This adds a common place to set the final opprefix, optype and opmenu, with a hook to override the opmenu. Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-04sb/intel/common: Use correct bitwise operatorJacob Garber
Like the line above it, this should be & instead of | (otherwise it will always incorrectly return true). spi_locked() is only used internally to decide which opcodes will be used to talk to the flash, and if it is falsely reported as locked, the worst case should be a denial of service (unless there are more bugs). Change-Id: I5208b523c815d15d7263594f06ccfacd8a9510b1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402092 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-28sb/amd/sb{700,800}: Clean up index manipulationsJacob Garber
It looks like in days gone by that these switches were once parts of loops that incremented 'index' as they went along. However, we don't have any loops anymore, so remove the needless increments and streamline the rest of the assignments. Change-Id: Iaabee984333c273af7810f9c11ed26bbb2a995d1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: scan-build 8.0.0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-28sb/amd/rs780: Remove dead assignmentJacob Garber
We return immediately after, so this assignment can be removed. Change-Id: I2a317ada0132a40b623402055b3b995bde80ddf5 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: scan-build 8.0.0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21sb/intel/common: Link SPI code in bootblockArthur Heymans
Change-Id: I2874bc37c6bceb2b22115a09ed1501ce917b4623 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-21sb/amd/sr5650: Use 32 bit integers when disabling portsJacob Garber
This function attempts to set bits in the 20s of state and state_save, which won't work since those variables are only 16 bits wide. Extend them to 32 bits to capture all the bit operations. Change-Id: I5616a2d879a85ff5f57af5af20384516659c62d6 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1347384 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-21sb/nvidia/ck804/lpc.c: Remove variable set but not usedElyes HAOUAS
Change-Id: I19b16bc2052440ca191cf3e30810ddc58a485a60 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33063 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21sb/intel/bd82x6x/early_pch.c: Remove variable set but not usedElyes HAOUAS
Change-Id: If359eaa010949427dbff1e3a83528c0ad399dc9d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32943 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetreeArthur Heymans
Set up generic decode ranges based on the devicetree settings. Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-21sb/intel/ibexpeak/smihandler: Move finalizing to a common locationArthur Heymans
TODO: There is no reason to do this in SMM. Change-Id: I8bbb2f65bbe674bd1bc4ae8a4086bd1f5e9a79fa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33139 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-20southbridge/intel/common/smbus: Add do_i2c_block_write()Frans Hendriks
Intel Braswell supports i2c block writes using SMBus controller. This support is missing in actual smbus routines. Add do_i2c_block_write() which is a based on do_smbus_block_write() but also write first byte to SMBHSTDAT1. The caller needs to configure the SMBus controller in i2c mode. In i2c mode SMBus controller will send the next sequence: SMBXINTADD, SMBHSTDAT1, SMBBLKDAT .. SMBBLKDAT To ensure the the command is send over the bus the SMBHSTCMD register must be written also BUG=N/A TEST=Config eDP for LCD display on Facebook FBG-1701 Change-Id: I40f8c0f5257a62398189f36892b8159052481693 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-19sb/nvidia/ck804/fadt.c: Remove unused LONG_FADTElyes HAOUAS
LONG_FADT is not used at all. So remove it and use sizeof(acpi_fadt_t) for header length. Change-Id: I433d1b2e0f3b9505d7c52eb14f1a476fbe52a284 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-06-19{mb,sb}: Use get_acpi_table_revision(FADT)Elyes HAOUAS
Change-Id: Id3d7f021a52e08906ae0a3f794756e397601fe96 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33428 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-19sb/intel/common/spi: Properly check if setting FRP succeededArthur Heymans
Change-Id: Ib0b63c3b0342c62aeabb5c6e418eb9811fc6597d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-18sb/amd/cimx/sb900: Change logical negation to bitwiseJacob Garber
data &= !BIT0 will clear data, since !BIT0 evaluates to 0 (oops). We only want to clear bit 0, not the whole thing, so use bitwise negation instead. Change-Id: I2179119e0d2d4aceaf4f8b499bf4c5baf4ef677f Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1241812 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-06-18sb/intel/bd82x6x/lpc.c: Remove reinitializing the SPI driverArthur Heymans
This was done to update the global variable g_ichspi_lock but this is now removed in favor of reading the lock bit during runtime instead of keeping track of the state. Change-Id: I8cb69a152b0e050d64d8979ee92de2d24136f8dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33390 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-18sb/intel/spi: Check for the SPI lock bit during runtimeArthur Heymans
The SPI swseq controller can be locked in other parts of the code, for instance when it's locked down in the finalize section. The driver has to be made aware of that. The simpler solution is to not keep track of the state and simply read out the lock bit on each SPI transfer. Change-Id: Ifcd5121b89d6f80fc1c1368786982d0d9fa1bf61 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-18sb/intel/common/spi.c: Add a pointer to the ich7 SPI registersArthur Heymans
Change-Id: I7509dc2124ee7057af075c7d0607ec615b930fa3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-18sb/common/intel/spi.c: Don't use typedefs for structsArthur Heymans
Change-Id: Id0ed621b5b4b5634d454811b1e1beeb27fc69ea8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-07sb/amd/sb700: Fix misleading formattingMarshall Dawson
Change-Id: I65872d6f1d71d050c8589d3616340648cf95048b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-06sb/intel/ibexpeak: Copy the sandybridge bootblock.c fileArthur Heymans
This allows to port C_ENVIRONMENT_BOOTBLOCK to sandybridge separately from nehalem. Change-Id: If3c6619cf22d1e2995eb19823b0f3f969d252b3b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-06sb/intel/i82801gx: Detect if the southbridge supports AHCIArthur Heymans
This automatically detects whether the southbridge supports AHCI. If AHCI support is selected it will be used unless "sata_no_ahci" is set in the devicetree to override the behavior. Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-05southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outwHannah Williams
outw takes (value, addr) not (addr, value) Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622 Signed-off-by: Hannah Williams <hannah.williams@dell.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-05sb/intel/i82801gx: Include chip.h directlyArthur Heymans
Change-Id: I3d743e90444292be687999ab4f50aa89d514fbad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33171 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03sb/intel/i82801ix: Select SOUTHBRIDGE_INTEL_COMMON_SPIArthur Heymans
This allows to use the CONFIG_CONSOLE_SPI_FLASH. Change-Id: I563c69ce6337d46380f889f42633e858ac207916 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-03sb//nvidia/mcp55/mcp55.c: Remove variable set but not usedElyes HAOUAS
Change-Id: I40cae58a7a7c9c3c20367541853001510a59e42b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33061 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03sb/nvidia/ck804: Remove variable set but not usedElyes HAOUAS
Change-Id: Ia8586e229e04fa11696a846653a3a54909ca7c1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-03sb/nvidia/mcp55: Remove variable set but not usedElyes HAOUAS
Change-Id: Ic8f6c264aedbdab0eacb6a99a32cc90336e08d84 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33011 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03sb/intel/fsp_rangeley: Remove variable set but not usedElyes HAOUAS
Change-Id: Ia2bc9bb0f0ece5ae3a57662b54f3e7e78ce00b19 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-29src/southbridge: Add missing 'include <types.h>'Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. When <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I4d8628e4ce3c7f80da2590b4cad618b290e0d513 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-29sb/intel/*: Delete early_spiPatrick Rudolph
The file and all of it's functions are unused. Drop the dead code. Change-Id: Iaddd7a688d431d40f38293939e084d19b286aed4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Guckian Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-27sb/intel/common/smi.c: Remove unused functionsArthur Heymans
Since all targets using sb/intel/common and cpu/intel/smm/gen1 are now using PARALLEL_MP, some code is not used anymore. Change-Id: Ibdc2bb0f1412366b945813efbc1b6451d27f376f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30019 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-27sb/intel/ibexpeak: Use common Intel SMM codeArthur Heymans
TODO in followup patch: Some not mainboard specific things should be moved out of mainboard_smi_apmc. Change-Id: Ifc2d8f7755ace598e66b162d071d472093e4656e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-25nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c. Tested on Foxconn D41S. Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-20sb/amd/cimx/sb800: Get rid of power button device in corebootPaul Menzel
Apply commit d7b88dcb (mb/google/x86-boards: Get rid of power button device in coreboot) to AMD Brazos boards [1]: > As per the ACPI specification, there are two types of power button > devices: > 1. Fixed hardware power button > 2. Generic hardware power button > > Fixed hardware power button is added by the OSPM if POWER_BUTTON flag > is not set in FADT by the BIOS. This device has its programming model > in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this > power button device by default if the power button FADT flag is not > set. > > On the other hand, generic hardware power button can be used by > platforms if fixed register space cannot be used for the power button > device. In order to support this, power button device object with HID > PNP0C0C is expected to be added to ACPI tables. Additionally, > POWER_BUTTON flag should be set to indicate the presence of control > method for power button. [..] > This change gets rid of the generic hardware power button from all > google mainboards and relies completely on the fixed hardware power > button. The same problem exists with the AMD Hudson devices in coreboot. For AMD Hudson (2) and Yangtze based devices this was removed in commit 44f2fab8 (AMD hudson and yangtze boards: Let mainboard declare power button) [2]. Two devices are detected. $ dmesg | grep Button [ 0.209213] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0 [ 0.209254] ACPI: Power Button [PWRB] [ 0.209332] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1 [ 0.209349] ACPI: Power Button [PWRF] $ sudo evtest No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Power Button /dev/input/event1: Power Button [..] [1]: https://review.coreboot.org/5546 [2]: https://review.coreboot.org/27272 Change-Id: I0cbecb72f7e1bf3d051d3b7656c6af4d6f43b497 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/27496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-05-16nb/intel/sandybridge: Move DMI init codePatrick Rudolph
Move the DMI initialization code to northbridge folder. Leave southbridge specific settings in bd82x6x folder and call it from northbridge code. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: Ib0b47391f3309f9ab0c3a3a8d525f38f8cca73c0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-16sb/intel/bd82x6x/early_pch: Make use of RCBA and DMIBAR marcrosPatrick Rudolph
Use RCBA and DMIBAR macros to get rid of DEFAULT_RCBA and DEFAULT_DMIBAR. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: Ic9be2240ea10b17c8cc289007dccadbb9e3f69ab Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-16sb/intel/sandybridge/early_pch: Make DMI init more readablePatrick Rudolph
Add a few comments and use known register values. Based on the "2nd Generation Intel® Core™ Processor Family Mobile" datasheet and the existing serialice trace. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to GNU/Linux. Change-Id: I404515b77a22324f55581f117d79630be4ba64dd Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32071 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-15src/southbridge: Remove unneeded include <arch/io.h>Elyes HAOUAS
Change-Id: If358e221021466f0058bfc84a322750b34a36d5f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-13i82801gx/bootblock: Use macro instead of magic numberElyes HAOUAS
Change-Id: I2556c150f53d9580bc3b70ab49b3a2c8477c18ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13{bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macroElyes HAOUAS
Use BIOS_CNTL defined macro instead of magic number. Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-12nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGENico Huber
We keep the support, though. Just now that `libgfxinit` is fixed, we don't need the distinction anymore. Causally, we also don't need CPU_INTEL_MODEL_306AX any more. TEST=Played tint on kontron/ktqm77. Score 606 Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-10sb/bd82x6x: Don't rewrite over BCTRLElyes HAOUAS
PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not apply to this PCI bridge because it is only defined for "Header type 0 (normal devices)" (line 82). Some lines obove that code line, the "write" on BCTRL is already done. Change-Id: I8f1b98ba627947ab6652a4ba31d2acb159dd3e32 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32700 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-10sb/i82801gx: Don't rewrite over BCTRLElyes HAOUAS
PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not apply to this PCI bridge because it is only defined for "Header type 0 (normal devices)" (line 82). BCTRL registry for D30:F0 is defined at offset 0x3e for i82801gx (see ICH7 Family Datasheet page 355). The write on that register is already done some lines above. So remove wrong register name and the wrong code line. Change-Id: Ib8a0514200f424049503bb8e4bc076ee6ae86ce3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-10nb/intel/i945: Use macro instead of magic numberElyes HAOUAS
Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31027 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-10sb/i82801gx: Remove duplicated 'define PMBASE'Elyes HAOUAS
Change-Id: If08bea821043bc8e661bf5327f4fe2cef3a65be8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07sb/intel/bd82x6x: Fix flashconsole after lockdownDan Elkouby
SMM final locks the SPI BAR, which causes flashconsole to hang. Re-init it like SMM does with CONFIG_SPI_FLASH_SMM. Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com> Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07sb/{ICH7,NM10,PCH}: Use common watchdog_off functionElyes HAOUAS
Change-Id: I704780b6ae7238560dcb72fc027addc1089e0674 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian
2019-05-06Fix code that would trip -Wtype-limitsJulius Werner
This patch fixes up all code that would throw a -Wtype-limits warning. This sometimes involves eliminating unnecessary checks, adding a few odd but harmless casts or just pragma'ing out the warning for a whole file -- I tried to find the path of least resistance. I think the overall benefit of the warning outweighs the occasional weirdness. Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06sb/amd/rs780: Use 32 bit variable to avoid truncationJacob Garber
The {read,write}_index functions expect a 32 bit value, as do the bitwise operations. Found-by: Coverity Scan #1229584 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Idc2bc46c899d5a4e8b089644dca076a88d97dd7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/32528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-06sb/intel/bd82x6x: Use common/rcba.hPatrick Rudolph
Make use of: * southbridge/intel/common/rcba.h * southbridge/intel/common/pmbase.c * defines in pch.h Get rid of dependency to DEFAULT_RCBA. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: I879fce6a5bb80499e1986e618a1422a7aaa3a0c0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32066 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-03{soc, southbridge} : Correct typo in commentFrans Hendriks
BUG=N/A TEST=N/A Change-Id: I1b207e0b77bac8860ba7501378297c1f3604141c Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32453 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-29sb/intel/bd82x6x: Use system_reset()Elyes HAOUAS
Use already defined system_reset() function. Change-Id: I6e5aff96e06830931acf700593d3e1689857efdc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-25src/southbridge/intel: Remove unused variablesElyes HAOUAS
Change-Id: I3b5092aa076b9693f78c86ffb9b99805696bb0bb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25src/southbridge/amd: Remove unused variablesElyes HAOUAS
Change-Id: I143f3395a385e170cce0979707d6a7f61107f40b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-23sb/intel/bd82x6x: fix linking for non-native raminit caseMatt DeVillier
Commit 45d4b17 [nb/intel/sandybridge: Move southbridge code to bd82x6x] moved early_pch_init() to the southbridge, but failed to include early_pch.c for the non-native raminit case, which now fails to link. As all boards default to native raminit, this was missed by the autobuilder. Adjust early_pch.c to be compiled regardles of ram init type used Test: build/boot google/stout with MRC ram init selected Change-Id: I50db30fda9a1099fb434c04ea97bcc38f8455233 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23sb/intel/lynxpoint: Enable LPC/SIO setup in bootblockArthur Heymans
This allows for serial console during the bootblock and enables console in general for the bootblock. Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30315 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23nb/intel/sandybridge: Drop pch.h from sandybridge.hPatrick Rudolph
Include pch.h in the source files instead in sandybridge.h. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23src: Use include <console/console.h> when appropriateElyes HAOUAS
Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-23sb/intel/i82801gx/lpc: Use {read,write}_pmbase32 and lpc_get_pmbaseElyes HAOUAS
Also use macros instead of magic numbers. Change-Id: I00bd687c487894c72d4e4363774dbcdfaf62dd54 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-21nb/intel/haswell: Add an option for where verstage startsArthur Heymans
Previously Haswell used a romcc bootblock and starting verstage in romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also possible to have a separate verstage. This selects using a separate verstage by default but still keeps the option around to use verstage in romstage. Also make sure mrc.bin is only added to the COREBOOT fmap region as it requires to be run at a specific offset. This means that coreboot will have to jump from a RW region to the RO region for that binary and back to that RW region after that binary is done initializing the memory. Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26926 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-21cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCKArthur Heymans
This puts the cache-as-ram init in the bootblock. Before setting up cache as ram the microcode updates are applied. This removes the possibility for a normal/fallback setup although implementing this should be quite easy. Tested on Google peppy (Acer C720). Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch, hence BOOTBLOCK_CONSOLE is not yet enabled by default. Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-18nb/intel/sandybridge: Move southbridge code to bd82x6xPatrick Rudolph
Move the southbridge code to bd82x6x folder similar to the lynxpoint implementation. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: I8afc9f966033f45823f5dfde279e0f66de165e93 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-16sb/intel/bd82x6x: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph
Use common code to detect ACPI S3. Tested on Lenovo T520 (Intel Sandy Bridge) with Change I8afc9f966033f45823f5dfde279e0f66de165e93 applied as well. Still boots to OS, no errors visible in dmesg and S3 resume is working. Change-Id: I283a841575430f2f179997db8d2f08fa3978a0bb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-16sb/intel/i82801ix: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph
Use common code to detect ACPI S3. Untested. Change-Id: I618d4c25adb0d2b9bbd59a3b3b84beac78db1916 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-13sb/intel/common: Fix config name in a commentNico Huber
This sneaked in after we made unknown arguments to CONFIG() an error. Change-Id: Ia1de78ce1d3277c7b094c3283455f4b56f3a3fbb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32314 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-13sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph
Use common code to detect ACPI S3. Tested on Thinkpad X60. Change-Id: Ia759a9ed141efc8130860300f2a8961f0c084d70 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-13sb/intel/lynxpoint: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph
Use common code to detect ACPI S3. Untested. Change-Id: I87ac56e4ba1fb83761786d5f32a0fc308ee9718a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32039 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-13sb/intel/i82801jx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph
Use common code to detect ACPI S3. Untested. Change-Id: I2264c087b317f70506817b5458295a17e83b1efc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32038 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-13sb/intel/common: Add common detect_s3_resumePatrick Rudolph
Add a common detect_s3_resume function. Will be used by other southbridge code. TODO: Merge with soc/intel/common/*/pmclib Tested on Lenovo T520 (Intel Sandy Bridge) with Change I283a841575430f2f179997db8d2f08fa3978a0bb applied as well. Still boots to OS, no errors visible in dmesg and S3 resume is working. Change-Id: I88023af522afac8164f068b0fbe0eac601aef702 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-07sb/intel/{common,i82801dx}: Improve TCO debug codeJacob Garber
Report unhandled TCO bits (previously dead code). This finishes the work done in 3e3b858 (sb/intel/ibexpeak: Update debug code to match other chips). Found-by: Coverity Scan, CID 1229598 (DEADCODE) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I65df8f3363c62b364e096368a36ba5e9e8894c13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32179 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-03-29src: Use include <reset.h> when appropriateElyes HAOUAS
Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-27Move calls to quick_ram_check() before CBMEM initKyösti Mälkki
After raminit completes, do a read-modify-write test just below CBMEM top address. If test fails, die(). Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 14:49:00 +0000