summaryrefslogtreecommitdiff
path: root/src/southbridge
AgeCommit message (Collapse)Author
2021-05-05sb/intel/lynxpoint: Fix VBOOT with !CONFIG_INTEL_LYNXPOINT_LPArthur Heymans
The Intel Basking Ridge CRB does not have a Lynxpoint LP PCH but was using the lp gpio code instead of the southbridge/intel/common code in verstage. Change-Id: I775d3dc3540fbd8a939701d873183dd016e24ba4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-27sb/intel/common: Refactor _PRT generation to support GSI-based tablesTim Wawrzynczak
Newer Intel SoCs also support _PRT tables, but they route PCI devices to more than just PIRQs, and statically specify IRQs instead of using link devices. Extend/refactor intel_acpi_gen_def_acpi_pirq to support this additional use case. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-26sb/intel/lynxpoint: Add and use power state bit macrosAngel Pons
Tested with BUILD_TIMELESS=1, Google Wolf remains identical. Change-Id: Id85b76c0aaf481f99f55a9ce6d813ff32753e588 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-21ChromeOS: Use CHROMEOS_NVS guardKyösti Mälkki
Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where the conditional and dependency are clearly about the presence of an ACPI NVS table specified by vendorcode. For couple locations also CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS). This also helps find some of the CONFIG(CHROMEOS) cases that might be more FMAP and VPD related and not about ChromeOS per-se, as suggested by followup works. Change-Id: Ife888ae43093949bb2d3e397565033037396f434 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21{sb,soc}/intel: Use `get_int_option` functionAngel Pons
Change-Id: I05f724785880089a513319d70dfd70fc2a6b7679 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-21sb/intel/bd82x6x: Use {get,set}_int_optionAngel Pons
Change-Id: Icbfea8c516c42b45d689da92b7e426cb6d5112a5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-21sb/intel/x/sata.c: Use `get_int_option` for `sata_mode`Angel Pons
Change-Id: Ifd1f3969281e67d1a6ab7eb99dd048799c0cb17d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-19sb/intel/common: Drop some PCH_LPC_DEV macrosAngel Pons
The macro definitions depend on __SIMPLE_DEVICE__ and are only used in the get_gpio_base() or lpc_get_pmbase() functions, which already guard PCH_LPC_DEV usage using __SIMPLE_DEVICE__ in preprocessor. Change-Id: I5d3681debe29471dfa143ba100eb9060f6364c93 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-11sb/amd/pi/hudson: remove unused Bolton PI FCH codeFelix Held
There is no nb/amd/pi northbridge left in coreboot that could be paired with the Bolton FCH, since the remaining nb/amd/pi northbridges all use an integrated FCH (Avalon on Mullins and Kern on Carrizo) while Bolton is a discrete FCH. I ran into this when verifying if the common soc/amd GPIO functionality that gets added by selecting SOC_AMD_COMMON_BLOCK_BANKED_GPIOS is valid for all chips selecting it and that code isn't valid for Bolton that uses the old GPIO 100 interface. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iffe876bee96e42645e1be10730b78959b1c06d59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52222 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-11sb/intel/x/smbus.c: Correct register access widthAngel Pons
The register is 16 bits wide. Change-Id: I58d44a17613965e0a27aab5246dcdce68e1a8201 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-06arch/x86: Provide readXp/writeXp helpers in arch/mmio.hAngel Pons
These p-suffixed helpers allow dropping pointer casts in call-sites, which is particularly useful when accessing registers at an offset from a base address. Move existing helpers in chipset code to arch/mmio.h and create the rest accordingly. Change-Id: I36a015456f7b0af1f1bf2fdff9e1ccd1e3b11747 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51862 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06sb/intel/i82371eb: Do not read PM/SMBus I/O ports at runtimeKeith Hui
Commit 023fdaffd1 (mb/asus/p2b: Refactor southbridge ACPI stuff) moved the southbridge ACPI stuff to its own file. It also (prematurely) listed PM and SMBus I/O port ranges as a #defined fixed value. Since these two ranges are not expected to change at runtime anyway, we can simply drop the ASL code doing the read. Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41093 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06sb/intel/*/smihandler.c: Correct BIOS_CNTL access widthAngel Pons
The BIOS_CNTL register is 8 bits wide on all affected platforms. Change-Id: Iaf9267cf27847d54ed50e1f9ae29011d0e99cf8e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51939 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25nb/intel/haswell: Move USB config API into Lynx PointAngel Pons
Both EHCI and xHCI USB controllers are inside the PCH (southbridge). Now that mainboard USB configuration no longer depends on pei_data.h definitions, the API declarations can be placed in southbridge code. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ia21991b225482b33c5bc0dc52884674d301b28ba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-24sb/intel/common: Use new acpigen_write_PRT_*_entry functionsTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I9f573b9bd40260ab963c5a4a965a6ac483af91ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/51158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-22{lynxpoint/broadwell}: Set Azalia HDCFG.BCLD bitAngel Pons
Lock down several HD Audio registers by setting the HDCFG.BCLD bit. Tested on Asrock B85M Pro4, the GCAP register becomes read-only. Change-Id: Id6208289a68baaedc4aad51cc0c5355f996a1b00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-22{lynxpoint,broadwell}/hda_verb.c: Drop effect-free writeAngel Pons
This bit is hardwired to 1 (Intel High Definition Audio mode). Change-Id: I3683497c5e2446f1d8319037583890b5d0a8a95c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-22sb/intel/lynxpoint/hda_verb.c: Add missing codec detect stepsAngel Pons
Lynx Point reference code version 1.9.1 and soc/intel/common/hda_verb.c perform these steps. Add them to Lynx Point as well. With this change, Lynx Point and soc/intel/common hda_verb.c files are now identical. Change-Id: I2fc592f73697a43bd5a3315ac80c77ff9f00da9b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-22mb/asus/p2b: Refactor southbridge ACPI stuffKeith Hui
Move (remaining) southbridge ACPI stuff into one file under sb/intel/i82371eb, that is simply included from the board's \_SB scope. Change-Id: Ibed49a800dec19534761e5ab22a6cbb1e6bd4a5d Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-22lynxpoint/broadwell: Rename LP GPIO config globalAngel Pons
Do not use the same name as the non-LP GPIO config. This allows checking at build-time that a mainboard uses the correct GPIO config format. Without this commit, there are no build-time errors when using the wrong format of GPIO config, but there would be undefined behavior at runtime. Tested by trying to build asrock/b85m_pro4 and hp/folio_9480m after toggling the `INTEL_LYNXPOINT_LP` Kconfig option (and trimming down the USB config arrays for asrock/b85m_pro4). In both cases, building failed because the necessary GPIO config global is not defined, as expected. Change-Id: Ib06507ef8179da22bdb27593daf972e788051f3a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51661 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22acpi/acpigen.h: Add more intuitive AML package closing functionsJakub Czapiga
Until now every AML package had to be closed using acpigen_pop_len(). This commit introduces set of package closing functions corresponding with their opening function names. For example acpigen_write_if() opens if-statement package, acpigen_write_if_end() closes it. Now acpigen_write_else() closes previously opened acpigen_write_if(), so acpigen_pop_len() is not required before it. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-15sb/intel/lynxpoint: Move S3 check out of `early_pch_init`Angel Pons
Done for consistency with other platforms. This also drops redundant S3 resume logging, as `southbridge_detect_s3_resume` already prints it. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: Id96c5aedad80702ebf343dd0a351fbd4e7b1c6c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-15sb/intel/lynxpoint: Replace HPET_ADDRAngel Pons
The `HPET_ADDRESS` Kconfig option has the same value. Use it instead. Change-Id: I268e949d4396aa20e38f719b36cc4e6226efe082 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-10nb/intel/haswell: Finalize northbridge in ramstageAngel Pons
There's no need to finalize the northbridge in SMM. This also makes unification with Broadwell easier. Tested on Asrock B85M Pro4, still boots and registers get locked. Change-Id: I8b2c0d14a79e4fcd2e8985ce58542791cef9b1fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-07sb/intel/lynxpoint/me.c: Reorder functionsAngel Pons
Rearrange the code to ease comparing against Broadwell. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3143f07ed845e0c6b1444817029a437db3b959e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-07sb/intel/lynxpoint: Finalize ME in ramstageAngel Pons
Performing ME finalization in SMM does not seem to be required. Tested on Asrock B85M Pro4, ME still gets finalized successfully. Change-Id: I9fde40a54f3fb8da2fba46c531443fdd2e067077 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-07sb/intel/lynxpoint/me.c: Use res2mmio()Angel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I87fa1ffb353135cc361ac6be30a4fc69e7f8ed47 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-03-07sb/intel/lynxpoint: Retype `mei_base_address` pointerAngel Pons
Also introduce uintptr_t cast and use PCI_BASE_ADDRESS_MEM_ATTR_MASK. Change-Id: I32fdcc6b1ffde1b0701218a3bd0a61ab827081b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-07sb/intel/common/pciehp: Replace HP dummy device with common codeArthur Heymans
Use the common PCIEXP_HOTPLUG code to generate a dummy device for PCIe ports supporting hotplug. This allows to have control over how much resources are allocated to hotplug ports. Tested on thinkpad X220: now hotplugging a dGPU via the expresscard slot sometimes works. Change-Id: I3eec5214c9d200ef97d1ccfdc00e8ea0ee7cfbc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph
2021-03-05sb/ti/pcixx12: Remove NOOP chip driverArthur Heymans
Change-Id: I46bc854239e723a1685279f634e635b72e7b3af9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-05sb/intel/lynxpoint: Refactor `usb_xhci_port_count_usb3`Angel Pons
Change the function parameters to avoid preprocessor usage. Change-Id: Iec43e057ed2a629e702e0f484ff7f19fe8a0311b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-05soc/intel/broadwell/pch: Use Lynx Point smbus.cAngel Pons
Continue unifying Lynx Point and Wildcat Point (PCH for Broadwell) code. Define the WPT-LP SMBus PCI device ID, add it to smbus.c of Lynx Point, and drop all now-unnecessary SMBus code from Broadwell. Change-Id: I864d7c2dd47895a3c559e2f1219425cda9fd0c17 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-03sb/intel/lynxpoint/lpc.c: Relocate lock bit writeAngel Pons
This lock bit can be set later, and should also be set for LynxPoint-H. This eases merging with Broadwell, which already sets this lock bit after `spi_finalize_ops()` in a dedicated finalisation function. Tested on Asrock B85M Pro4 (LynxPoint-H), the lock bit is now set. Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47036 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01sb/intel/bd82x6x: Turn ME PCI register structs into unionsAngel Pons
This allows dropping the `pci_read_dword_ptr` and `pci_write_dword_ptr` wrappers. Change-Id: I7a6916e535fbba9f05451d5302261418f950be83 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49993 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01sb/intel/lynxpoint/me_9.x.c: Rename to me.cAngel Pons
This code will eventually support both ME 9.x and ME 10. Change-Id: Idc02ab668a0b0d51c31f33f1266d983e64fb5505 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-27sb/intel/ibexpeak: Drop useless bd82x6x pcie.cAngel Pons
The PCIe device IDs for Ibexpeak are not in bd82x6x's pcie.c driver. Thus, the code has always been dead code on Ibexpeak. Drop it. Change-Id: Ide2b4af2a187ecf98f39a9c979646a7ed959c74f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51067 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27sb/intel/ibexpeak: Add all PCI IDs for LPCAngel Pons
Taken from document 322170-028 (5 series specification update). Tested on out-of-tree HP ProBook 6550b (HM57), fixes several issues. Without this patch, EHCI controllers had no IRQ assigned and there were unexpected exceptions about NMIs. With this patch, the issues are gone. Change-Id: Icd31dd89ba49e38a5e4c108a8361dbf636332ab8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51066 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1Angel Pons
Add the missing PM initialization for Lynxpoint-H. There are some small changes to Lynxpoint-LP, since some register writes are common among both PCH variants. This is based on version 1.9.1 of reference code. Remove the `pch_fixups()` function. The DMI configuration is specific to Lynxpoint-H. It is not valid for Lynxpoint-LP, which does not have DMI. Tested on Asrock B85M Pro4, still boots. Registers have the new values. Without this patch, nearly all registers don't have the expected values. Change-Id: Ie3f96f2106f3c23aeb694dd6fb343099fc5784e5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47208 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-25sb/intel/lynxpoint/acpi: Add missing USB portsAngel Pons
Broadwell has these devices, so add them to Lynx Point as well. This is done in preparation to have Broadwell boards use Lynx Point ACPI code. Change-Id: Id66f169070cdfe3a6d166ca18916d4ddaf4a5fea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46959 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-25sb/amd/agesa/hudson/lpc: Remove space between function and signaturePaul Menzel
Change-Id: I4dd40014259ac3fd0223f7feb08620b87735f60b Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25sb/amd/agesa/hudson: Use comment style from style guidePaul Menzel
Change-Id: I73d713ec3aa62ae207640ac7e5550e5407f5afa2 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23sb/amd/common: Drop dummy variable assigmentKyösti Mälkki
Change-Id: I9b523bda2332859074d2e12c5cb70df68e18063d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-23sb/intel/lynxpoint: Refactor some GNVSKyösti Mälkki
Change-Id: I9524a44f8f4b8e286229d81d10704438f11c4580 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22Revert "lynxpoint: Fix SerialIO ACPI compile issue with recent IASL"Angel Pons
This reverts commit 1a25c9cdfd3fd391328133ba94c63ecd1083e4f8. Reason for revert: No longer necessary. Change-Id: I8adeeebd6e841ef2c878622559dcd15848969842 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46955 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-20ACPI: Use common OperationRegion for PCI_MMCONFKyösti Mälkki
Change-Id: Iadb4c3c77ecda4df8e48415d246e769ede2ce86d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50648 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-20sb,soc/amd: Drop OSFL method in ASLKyösti Mälkki
Variable OSVR had a static value of 3 and OSFL() did not actually call _OSI or _OS methods. The conditional in HDA _INI method of OSVR is dropped and use of DMA NoSnoop attribute remains disabled to retain previous behaviour. For soc/amd/picasso a different decision was made in CB:40782 as HDA _INI method was just dropped and default configuration enables use of DMA NoSnoop attribute. Change-Id: I967b7b2afbb43253cccb4b77f6c44db45e2989e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50592 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-20sb/amd/cimx/sb800: Drop OSFL method in ASLKyösti Mälkki
Method only set variable OSRV, which nobody evaluates. Change-Id: Ia21b544eaaa61a8fc634eb568b4c7401a225eb76 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-18southbridge: Ensure common Kconfig gets included lastAngel Pons
Change-Id: Icaa64e664499090fec3e98687b4827ef27cc201b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-18sb/intel/ibexpeak: Drop obsolete SATA register settingsAngel Pons
Code was copy-pasted from older chips and has no effect on ibexpeak. Change-Id: I3c5b2b8e4aa6211975c3e3dc1d64432886ef9352 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47864 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18sb/intel/lynxpoint: Correct read width in RMW cycleAngel Pons
The register is 32 bits wide, so do not read 16 bits out of it. LynxPoint PCH reference code version 1.9.1 always uses 32-bit accesses. Change-Id: I18fbba0603579417e09ae4eb4eb273f7fcd903fc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47098 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16sb/intel: Add missing <types.h>Elyes HAOUAS
Add needed but missing <types.h>. Change-Id: I19d01e1837b1ee946c66d4cc22a5138b64d72078 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50577 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16sb/intel/*/lpc: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: I8f8655853fd1fc1f3679a4549fdaa08702f96c7b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-15sb/amd: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: I8c0a40a14d0a9050b83fe5e9988db70b7f94b81c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50531 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/auron/var/buddy: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Google Buddy remains identical. Change-Id: I6e6256a9cc88c9d0743150bfdf12b1b482fe157d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50070 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15sb/intel/lynxpoint: Clean up lp_gpio.hAngel Pons
Move `mainboard_gpio_map` declaration inside header and reorder some function declarations. This is to align the header with Broadwell. Change-Id: I436d7fdabf8d574e5dd2787fb6097f384cc8e453 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50065 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14sb/amd/cimx/sb800: Move common OSFL method in ASLKyösti Mälkki
We deal with mb/lippert/frontrunner-af later since it currently does not include <cimx/sb800/acpi/fch.asl>. Change-Id: I30b611fc1fb01777223d7222adc96308a247a35c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50591 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14ACPI: Move common _PIC methodKyösti Mälkki
Change-Id: I659835354570fb1d4860fcbddf2a51831170a374 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-14sb,soc/amd: Drop empty CIRQ call from _PICKyösti Mälkki
Change-Id: Iaa51e0530a3f72456d3d4e7a0c55b768ba63e322 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49904 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14sb/amd/cimx/sb800: Drop CIRQ method from _PICKyösti Mälkki
Change-Id: Ie4aad7b6580100377c12f128905f7f409bdb5295 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50590 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14sb,soc/amd: Move _PIC method to global scopeKyösti Mälkki
Fix regression with commit aa969e887a ACPI: Move PICM declaration. While mentioned in the commit message there already, the default value for AMD boards changed from IOAPIC mode to PIC mode. ACPI 6.3 spec has this text regarding _PIC method: If the platform CPU architecture supports PIC mode and the method is never called, the platform runtime firmware must assume PIC mode. If MADT has IOAPIC entries, OS will want to change to APIC model. But the method _PIC was not in the global scope so it could not be called and therefore _PRT continued to report PIC model interrupt routing. Already fixed for soc/amd/picasso in commit 839f668. Change-Id: I7f3bb0d45946cec315694de1d540fea4d828348e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-13sb/intel/bd82x6x: Clean up early_me.c cosmeticsAngel Pons
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: I0dfbaaf4cb17841de109ea6abc08022846b5bd4e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49994 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13sb/intel/bd82x6x/me_smm.c: Deduplicate finalisation codeAngel Pons
The only difference between ME7 and ME8 is the MKHI message handling. Remove duplicated code, and also clean up includes. Change-Id: Ia44eb29d3509eb4208ba2aed9e0cf7e8f8d2c41a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49992 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13sb/intel/bd82x6x: Move ME SMM code into a separate fileAngel Pons
This allows dropping some preprocessor usage. The `mkhi_end_of_post` static functions had to be renamed to avoid a name clash. A follow-up will tidy up the code in me_smm.c to reduce some duplication. Change-Id: I6357fed3540be87f42d1fd59534666b9092d0652 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49991 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13sb/intel/bd82x6x: Relocate some static functionsAngel Pons
This allows us to get rid of the `__unused` attributes. Subsequent commits will separate ramstage and SMM code into separate files. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: I1aaef5aa23561bee04f8dd9ddca66738bca91bb4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49990 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13sb/intel/bd82x6x: Use HPTS() for HPET visibilityKyösti Mälkki
Platforms with bd82x6x do not initialise OSYS, so HPET is always hidden. The two boards lenovo/x201 and packardbell/ms2290 using sb/intel/ibexpeak but still including <bd8x62x/acpi/lpc.asl> initialised OSYS using _OSI() method and showed HPET selectively. Change-Id: I02fffd439be2a5a9d22afd67e68abce888361214 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49486 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13intel/broadwell,lynxpoint: Use HPTS() for HPET visibilityKyösti Mälkki
Platforms do not initialise OSYS so HPET is always hidden. Change-Id: I5f030b156355ea407d37cdb2eda8a3161085436f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-13sb/intel/i82801jx: Use HPTS() for HPET visibilityKyösti Mälkki
Change-Id: I741d94341ed59f5b5fbb8526205e8b502764a15a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50481 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13sb/intel/i82801gx,ix: Use HPTS() for HPET visibilityKyösti Mälkki
Change-Id: Id38228265ad89e3f96ea6f37bcc0da574a3f8c3f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49484 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13sb,soc/intel: Add HPTS() for HPET visibilityKyösti Mälkki
Based on the detected OS the HPET ACPI device needs to be hidden sometimes. Change-Id: I4c6f87f30ea0de5c073b1fcf57794bb9e19d4d91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49483 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12sb/intel/x/lpc.c: Drop commented-out `gpio_init` callAngel Pons
Change-Id: I4255c63f87e8243237204ac86eb85e34b5aaa225 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-12sb/intel/x/lpc.c: Drop `pch_disable_smm_only_flashing`Angel Pons
The southbridge common SPI support already does this. Tested on Asrock B85M Pro4, internal flashing and MRC cache still work. Change-Id: I7ce0ca584cd3d42a10cdb74f45742f1eadc01bfa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-12sb/intel/lynxpoint: Do not mask out TCO status bitsAngel Pons
Not all TCO status bits have a corresponding enable bit. Masking out the status register with the enable register causes these events to be lost. Tested on Asrock B85M Pro4, BIOSWR_STS events are now detected. Change-Id: I49abb5a4a99e943e57e0aaa6f06ff63bdf957cd3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-12sb/intel/lynxpoint: Only generate SerialIO SSDT for PCH-LPAngel Pons
Lynxpoint PCH-H does not have SerialIO, so do not generate its SSDT. Change-Id: Ie816ebd470df93a45826498bf21be59ff0a813bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12sb/intel/lynxpoint/pch.h: Guard macro parametersAngel Pons
Guard against unintended operator precedence and associativity issues. Tested on Asrock B85M Pro4, still boots. Change-Id: I2b22af17816e5383c7eb215a773eb6750d4ed9bc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12sb/intel/common: Move named packages out of methodAngel Pons
IASL complains that creation of named objects within a method is highly inefficient. Avoid this by moving these named objects out of the method. Change-Id: Iabfb20dcb3f655658844d99ab7a3b479684d9d19 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-11sb/intel/ibexpeak: Drop Global NVS supportAngel Pons
Was copy-pasted from bd82x6x and no mainboard actually needs it. The few globals moved outside the GNVS will be removed, relocated or replaced with acpigen later. Change-Id: I590a355f1bd1e54365b2e329cfdc62384446a15c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49280 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11sb/intel/i82801jx: Drop Global NVS supportAngel Pons
Was copy-pasted from i82801ix and no mainboard actually needs it. Change-Id: I400424540b52dc5d43aba15720b18ad57ea2ebda Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49279 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11ACPI: Move PICM declarationKyösti Mälkki
Variable PICM was not inside GNVS region and can use a static initialisation value. For most AMD platforms PICM default changes from 1 to 0. Fix comments about PICM==0 used to indicate use of i8259 PIC for interrupt delivery. Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11sb,soc/intel: Drop OSYS from GNVSKyösti Mälkki
The value should be set by OSPM using some combination of _OSI() queris in the \_SB._INI() method. To maintain previous behaviour with this commit, boards where GNVS osys initialisation was removed now do the same in ASL. Change-Id: Id4957b12a72fbf7fa988e7ff039e47abcc072e1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49353 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11mainboards: Drop PWRS from GNVSKyösti Mälkki
Initialize variable to 1 to indicate AC power supply. If platform has EC it will set this correctly based on whether plugged on the charger or not. Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11sb/amd/agesa/hudson/acpi/fch.asl: Sync whitespaceElyes HAOUAS
Make it look more like the file under amd/pi/hudson. Change-Id: I5b40dc5b6f54bf68113826e693ca5963fec83d38 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-11sb/intel/common/rtc.c: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: Ie11fffdf907227ab315bfd4887aaa5de3602bd24 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-11sb/amd/agesa/hudson/amd_pci_int_defs.h: Fix commentsAngel Pons
Change-Id: Iff701d8e6d672b3ca97d9d6361ba48736c06c6c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-02-11sb/amd/agesa/hudson: Drop setting `ACPI_FADT_RESET_REGISTER`Angel Pons
It is already set in `src/arch/x86/acpi.c` function `arch_fill_fadt`. Change-Id: Ica7e112ca253d1332ed2ea414948c8f1970d0a69 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-02-11sb/amd/agesa/hudson/sm.c: Drop unused `BITx` macrosAngel Pons
Tested with BUILD_TIMELESS=1, Lenovo G505s remains identical. Change-Id: I759bdef44f7ca0f35350901998f6820820005b38 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-11sb/amd/pi/hudson/pci.c: Remove empty init operationAngel Pons
Change-Id: I5620867b3044936be8ad1bf95255be5a3565bb51 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-02-11sb/amd/pi/hudson/imc.c: Remove duplicated commentAngel Pons
Change-Id: Ie2de3948a78352bbb68c9215222b8489cacb91ce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-02-10sb/intel/bd82x6x/acpi: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Ib587d7a982852e7123e43337407ef20d96811719 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntaxElyes HAOUAS
Also, fix typo on "success". Built gizmosphere/gizmo generate identical 'build/dsdt.dsl'. Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10sb/amd/pi/hudson/acpi/fch.asl: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ie413f36ef11a42a23d7d265d7a66f5e0d088892e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
Drop unused sandybridge.h includes to avoid build failures on Ironlake. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: If2f0147fe50266e2fe2098cafdf004e51282f5e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10sb/amd/common/acpi: Convert 'sleepstates.asl' to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I16919a0fd5a78d666dc7003d4e495fd41c24613d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10sb/amd/{agesa,pi}hudson/acpi: Convert 'pci_int.asl' to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I1a382eaf122e40aeaefedf88425749616a2090d9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10sb/amd/{agesa,pi}hudson/acpi: Convert 'AmdImc.asl' to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ica6998026031e1b3d7286ce74a2334237d29ac74 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10sb/amd/agesa/hudson/acpi/fch.asl: Convert to ASL 2.0Elyes HAOUAS
Change-Id: I8903450b505701e1fd62c1a70b896a4dfb37d5a1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10sb/amd/{agesa,pi}/hudson/acpi: Convert 'audio.asl' to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I976b4c2e2aa878d8b591c3e416ffb76d7a699b39 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45863 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09sb/intel/i82801{dx,ix,jx}/lpc.c: Fix typo in commentElyes HAOUAS
Change-Id: Id7110bb2229e7c8f5f49aae40cfdf50719d0fa25 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09sb/amd/pi/hudson/acpi/lpc.asl: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Id50b9a0f0e3f90f5288b420280d762b8a86a6527 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-08soc/intel: Guard TRAP method in ASLKyösti Mälkki
Needed to support build with ACPI_SOC_NVS=n as SMIF object inside GNVS disappears then. Change-Id: Ib798187c24996b74d6345080f7d48c3f657eb512 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07sb/intel/bd82x6x: Support ME Soft Temporary Disable ModeEvgeny Zinoviev
- Add support for ME Soft Temporary Disable Mode. In this mode, ME doesn't load its kernel and freezes at Bring UP (BUP) phase. This mode is saved in ME NVRAM (and thus will remain for next reboots and poweroffs). - Add support of new CMOS option for Sandy Bridge and Ivy Bridge ThinkPads. HOW TO USE To disable ME: 1. nvramtool -w me_state=Disabled 2. reboot To enable it back: 1. nvramtool -w me_state=Normal 2. reboot To check current status: intelmetool -m Tested on ThinkPad X230 and ThinkPad X220. BACKGROUND There's no Intel documentation that would explain how this should be implemented, in public. Working binary sequence for MKHI command to put ME in Soft Temporary Disable Mode, as well as a way to bring ME out of it (by writing to H_GS register), was found and published by researchers from PT Security: 1. To disable ME, BIOS issues the disable command (before End of Post) and reboots. ME is supposed to be disabled on the next boot after DID (DRAM Init Done). My numerous tests show that issuing the command and rebooting is not enough. If we reboot too early, ME will not be disabled. Apparently, it is doing something in background after receiving the command. It works with a delay of 500-1000 ms. I also tried to dump all known (documented) registers, such as GMES and HFS, before and during the next 2 seconds after execution of the disable command to find a possible indication that something's changed in ME and we're ready to reboot. Found nothing unfortunately. 2. To enable ME back, host writes value 0x20000000 to H_GS. PT slides don't contain any more information on it, but my tests show, that after writing this value, GMES[31:28] is changing from 0x01 (BUP phase) to 0x03 (Policy Module) to 0x06 (Host Communication). Then, after some more time, fw_init_complete bit of HFS becomes 1. This means that ME starts loading its kernel immediately, without reboot. On the other hand, Lenovo BIOS clearly perform a reboot after enabling it (one reboot after saving the settings, then ThinkPad logo appears, and then one more reboot). I'm assuming we have to reset too. Change-Id: Ic01526c9731cbef4e8552bbc352133a2415787c2 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 05:57:37 +0000