summaryrefslogtreecommitdiff
path: root/src/southbridge
AgeCommit message (Collapse)Author
2014-01-09bd82x6x/ibexpeak: Make DRAM reset gate GPIO configurableVladimir Serbinenko
DRAM reset gate GPIO is different on different mobos move it to hidden config with 60 (current value) as default. Set it to 10 for Lenovo X201. Change-Id: I4f3b6876d7c33d4966315091b63a76a9a0064c16 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4622 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-06usbdebug: Fix hidden menuconfig optionsKyösti Mälkki
Options for selecting the USB port and controller for usbdebug were unintentionally hidden with commit 8232bc2c on AGESA platforms using cimx/sb700 or cimx/sb800. Change-Id: Ibacc81a580519fe7fa86f08374046625327340b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4607 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-06nehalem: Simplify smi.c by using __SIMPLE_DEVICE__Vladimir Serbinenko
Change-Id: Ib5bac45ee7aa5492c10fa97cd75b828b6192250d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4604 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-12-29AMD fam10: Drop RAMINIT_SYSINFOKyösti Mälkki
AMD fam10 raminit cannot be built without RAMINIT_SYSINFO, this is not a true option but copy-paste remainder from AMD K8. Change-Id: Id8edc112f3bacebd1732304ac9ee6e77cc6263b7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-27via: Write »access« without »m« at endPaul Menzel
The comment was copied around so fix all occurrences using the following command. $ git grep -l accessm | xargs sed -i 's/accessm/access/g' Change-Id: I46e117c126c0f851cd5e95cf9e42a77ca5f80996 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4577 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-24Remove PCI_ROM_RUN optionVladimir Serbinenko
The main purpose of option rom is to supply int* handlers. But supplying those is outside of coreboot scope and if someone needs those they should run SeaBIOS anyway which runs the option roms wonderfully. Running VGA oprom is kept because they're needed to init graphics. This patch still keeps the options to include the option roms to make them available to SeaBIOS. Change-Id: I646334cf88094d3bf8f527779a68a07e0b4b93ec Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4545 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2013-12-23Coding style: punctuation cleanup [1/2].Idwer Vollering
Clean up superfluous line terminators. Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4562 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-22vortex86ex: Change PCI S/B resource reservation functions for more I/O devices.Andrew Wu
Originally, Vortex86EX PCI S/B internal resource reservation functions can only support one big legacy I/O device space (0-0xfff). Change function signature to support other non-legacy I/O device space in the future. Change-Id: I22f5c877ed441d59f29801d925ee40b24fb796ce Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3976 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-21lynxpoint: XHCI: Don't put device in D3 in _PS0 MethodDuncan Laurie
The end of the _PS0 method that is supposed to transition the XHCI device to D0 state is instead putting it in D3 state. This triggers a PME_B0 GPE which causes a Notify to the XHCI ACPI Device in the kernel and that increments the wakeup counter and causes aborted suspends. Instead if we just leave the device in D0 where it should be after executing this function then the PME_B0 is not generated and the kernel does not see a wakeup on XHCI. Similarly I changed the _PS3 method to always put the device in D3 at the end of the method, rather than depending on the state to be D3 at the start. Before this change the kernel would see the following sequence when trying to suspend when the XHCI controller is in D3cold: kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff88017802bf28) kernel: evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [XHCI] (Device) Value 0x02 (Device Wake) Node ffff88017802bc30 kernel: evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [EHCI] (Device) Value 0x02 (Device Wake) Node ffff88017802b8e8 kernel: evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [HDEF] (Device) Value 0x02 (Device Wake) Node ffff88017802b1b8 kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0 kernel: xhci_hcd 0000:00:14.0: PME# disabled kernel: xhci_hcd 0000:00:14.0: enabling bus mastering kernel: xhci_hcd 0000:00:14.0: setting latency timer to 64 kernel: PM: Wakeup pending, aborting suspend kernel: last active wakeup source: 0000:00:14.0 Now it does not get a notification (due to PME_B0) when going to D0 on the way into suspend. XHCI goes from D3cold to D0 (in order to be able to read mmio) and then back to D3hot before suspend. kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff88017802bf28) kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0 kernel: xhci_hcd 0000:00:14.0: PME# disabled kernel: xhci_hcd 0000:00:14.0: enabling bus mastering kernel: xhci_hcd 0000:00:14.0: setting latency timer to 64 kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._S3D] (Node ffff88017802c000) kernel: xhci_hcd 0000:00:14.0: PME# enabled kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS3] (Node ffff88017802bf50) kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D3hot Change-Id: Id5cd28eede2b27d97640047feb17349ae4ab79b7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65236 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4448 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: Fix an issue clearing port change status bitsDuncan Laurie
The coreboot and ACPI code that clears USB3 PORTSC change status bits was not properly preserving the state of the PED (port enabled or disabled) status bit, and it could write 0 back to this field which would disable the port. Additionally add back the code that resets disconnected USB3 ports on the way into suspend (as stated in the BWG) but take care to clear the PME status bit so we don't immediately wake. suspend/resume with USB3 devices 1) suspend with no devices, plug in while suspended, then resume and verify that the devices are detected 2) suspend with USB3 devices inserted, then suspend and resume and verify that the devices are detected 3) suspend with USB3 devices inserted, then remove the devices while suspended, resume and ensure they can be detected again when inserted after resume Change-Id: Ic7e8d375dfe645cf0dc1f041c3a3d09d0ead1a51 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65733 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4473 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: XHCI: Advertise D3 as lowest wake stateDuncan Laurie
The recommended value in docs is D2, but lynxpoint XHCI does not even support D2 state which causes the kernel to think this device cannot be used as a wake source: kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI kernel: ACPI: Device does not support D2 kernel: xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI Additionally this means the kernel will never put the device into D3 state by itself. There is SMI code that will put the device into D3 before suspend so advertising D3 here should be correct. With this change the kernel will put the controller into D3 on suspend and back to D0 on resume, including executing the ACPI methods for _PS0/_PS3 that contain chipset specific workarounds. In addition add a _PSC method to directly return the D state from the device registers. With ALL USB devices removed the XHCI controller goes into D3 state and the kernel can have a hard time determining the state of the device at boot. A kernel compiled with CONFIG_ACPI_DEBUG=y and module parameters acpi.debug_layer=0x7f acpi.debug_level=0x2f can be used to see what ACPI methods are executed: kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS3] (Node ffff8801000a7f50) kernel: ACPI: Preparing to enter system sleep state S3 ... kernel: ACPI: Waking up from system sleep state S3 kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff8801000a7f28) kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0 Change-Id: Ic64040eb4dd1947a1e2f0ee253a64be683e0ec70 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> meld with s3d Change-Id: Ic6789720c4efe661dcb03a4afce8d88115854472 Reviewed-on: https://gerrit.chromium.org/gerrit/63916 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4409 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: Fix issues with XHCI initDuncan Laurie
- Put the device into D0 and not D3 so memory bar is available and the subsequent commands actually do something useful - Remove set of 818Ch[7:0]=FFh (gone in ref code) - Fix reg 0x40/0x44 mixup Verify that expected bits are set: localhost ~ # pci_read32 0 0x14 0 0x10 0xe0500004 localhost ~ # mmio_read32 0xe0508144 0x000003ff localhost ~ # mmio_read32 0xe050816c 0x000f0038 Change-Id: I388398e8c7d11e538ca18dab55d8bbd9b88f17df Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63801 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4408 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: Route all USB ports to XHCI in finalize stepDuncan Laurie
This commit adds a new Kconfig option for the LynxPoint southbridge that will have coreboot route all of the USB ports to the XHCI controller in the finalize step (i.e. after the bootloader) and disable the EHCI controller(s). Additionally when doing this the XHCI USB3 ports need to be put into an expected state on resume in order to make the kernel state machine happy. Part of this could also be done in depthcharge but there are also some resume-time steps required so it makes sense to keep it all together in coreboot. This can theoretically save ~100mW at runtime. Verify that the EHCI controller is not found in Linux and that booting from USB still works. Change-Id: I3ddfecc0ab12a4302e6034ea8d13ccd8ea2a655d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63802 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4407 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: Move USB SMI sleep code to separate USB filesDuncan Laurie
Move this to the existing USB source files so they can share some helper functions and keep the main smihandler code cleaner. The XHCI sleep prepare code now implements the actual sleep preparation steps from the ref code instead of the docs. Change-Id: Ic90adbdaba947a6b53824e548c785b4fb3990ab5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63800 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4406 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: Add configuration option for SATA gen3 DTLE registersShawn Nematbakhsh
Allow DTLE DATA / EDGE registers to be configured in board-specific devicetree. Change-Id: I82307d08c9cf73461db3ac7fb875a4fe70d6f9ea Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65716 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4475 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21haswell: Misc updates from 1.6.1 ref codeDuncan Laurie
These programming sequences were changed in the latest code. Change-Id: Ia4b763a49542635713d11a9ee81f7e7f200bf841 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65612 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4466 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: Add devicetree config option to force enable ASPMDuncan Laurie
The PCIe root port has ASPM settings/workarounds that are only applied based on the value of an undocumented bit in PCI config register 0x32C. If that bit is not set for some reason then the settings are not applied. This devicetree config option will force the ASPM settings for each port based on the bit map. Change-Id: I40b08ca9a0ef52742609bac72fb821454a373799 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65314 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4453 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: me: Disable some verbose messagesDuncan Laurie
The default ME output is quite verbose and not all that useful unless you are actively debugging the ME and then you can enable the CONFIG_DEBUG_INTEL_ME option. This commit silences the firmware capabilities and the MBP output. Change-Id: I2b8abcb34ae0d00d9a38d029979e84ee0d0ca287 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65252 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4452 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: me: Support ICC clock enables messageDuncan Laurie
This message allows unused clocks to be disabled based on a devicetree setting in each mainboard. Change-Id: Ib1988cab3748490cf24028752562c64ccbce2054 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65250 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4450 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: me: Allow for more than MKHI MEI messagesDuncan Laurie
The original ME code was assuming that the only type of messages it would send were MKHI type and so it had some embedded checks for that header and that type of message. In order to support ICC messages this needs to change to handle different header types, so now the header will be sent first and then the data will follow, rather than the two both being sent in the same low-level function. This change has no real affect on the system, subsequent commit will add new ICC messages. Change-Id: I52848581e49b88c0a79e8bb6bda2a179419808a3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65249 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4449 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: Avoid any ME device communication in S3 pathDuncan Laurie
The management engine is occasionally hanging the system on resume when it is accessed. Since we actually don't need to do anything with it on resume it can be disabled early in the resume path and avoid assigning resources just to remove them later. suspend/resume on falco and check /sys/firmware/log to ensure that device 00:16.0 is disabled early and that no resources are probed or assigned and that the device init path does not execute. Change-Id: I35573681e3a1d43d816d24954842cbe9c61f3484 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62897 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4376 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint me: add support for mbp clear wait in finalize stepDuncan Laurie
The management engine is slow, requiring at least 500ms between when the Dram Init Done message is sent (right after memory training) to when the MBP will report that it is successfully cleared and that the ME can finally be sent the EOP message. Currently this is adding 100-150ms to the boot time. If we defer waiting for the MBP Clear indicator until the finalize step we can gain back that lost time. boot on falco with SMI debugging enabled to ensure that the ME is locked down in the finalize step: Finalizing Coreboot SMI# #0 SMI_STS: PM1 APM ME: MBP cleared ME: mkhi_end_of_post ME: END OF POST message successful (0) Change-Id: Icab4c8c8e00eea67bed5e8154d91a1eb48a492d1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62633 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4375 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint xhci: Add ACPI D0/D3 workaroundsDuncan Laurie
There are specific programming requirements for the usb3 ports on all LynxPoint chipsets when transitioning to D0 or D3. LynxPoint-LP has additional workaround steps needed involving resetting the disconnected ports when transitioning to D0. The workarounds are implemented in ACPI code so the controller can transition properly into D3 at runtime. Change-Id: I3b428562f48c9cb250b97779a3b2753ed4f81509 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62632 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4374 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Revert "lynxpoint: Move ME lock down to ramstage"Duncan Laurie
This reverts commit ff81f50f0e4c068b64c4a5c7f5244196ecd24965. Deferring this step until the finalize stage will allow us to defer waiting for the MBP clear indicator and speeding up the boot. Change-Id: Ib8edffd06689e72875830cd68b5aedb7ac3b0559 Reviewed-on: https://gerrit.chromium.org/gerrit/62631 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4373 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: power management setup tweakDuncan Laurie
Updated from 161 ref code Change-Id: I3e07935fec1df21f14d97d165792fe54bf9e474c Reviewed-on: https://gerrit.chromium.org/gerrit/62128 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4372 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint: Add LPT-LP device id and smbus_write_byteDuncan Laurie
This is needed for SMBUS drivers to write to devices. It was copied from existing intel southbridge driver. Change-Id: Id0ce2393b2946a9c741413bca563a1a4dc0a4f5e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61893 Reviewed-on: http://review.coreboot.org/4364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-18lynxpoint: Don't write to non-existent EHCIDuncan Laurie
The LynxPoint-LP chipset only has one EHCI controller so we should not attempt to write into the second one that only exists on LynxPoint-H. Change-Id: I1eae060c7f0a5873c9684e5abfeea5cb5895ab62 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63799 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4405 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12HDA: Enable Mini-HDA and fix up PCH-HDA initDuncan Laurie
The SystemAgent contains a mini-hd audio controller at PCI 0:3.0 which uses the same verb table init sequence as the southbridge. In order to avoid two copies of the verb table loading code I separated out the HDA verb table functions into a file that can be re-used and then added a minihd driver to the haswell northbridge. The minihd verb table is the same across devices so it can live within the minihd driver rather than needing to be specified in each separate mainboard. I also fixed up the driver for lynxpoint HDA by following the reference code. Without HDMI cable plugged in driver does not find any codec, and it does not seem to re-probe when HDMI is connected. We may be missing kernel patches for this. hda-intel 0000:00:03.0: no codecs found! With a basic kernel patch to add 0x0a0c device ID to HDA driver and with HDMI cable connected it is much happier: snd_hda_intel 0000:00:03.0: irq 60 for MSI/MSI-X input: HDA Intel MID HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input9 snd_hda_intel 0000:00:1b.0: irq 61 for MSI/MSI-X input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input10 input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input11 Change-Id: Ifa587984be4fc2801704a0368b9cdf8379c2450e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59336 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4318 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12peppy: Disable audio codec enable GPIO in S3 + S5.Shawn Nematbakhsh
To save power, disable audio codec in S3 + S5. Also, refactor Lynxpoint GPIO code slightly to allow usage in SMM binary. Change-Id: I55c4248c89a258b5e4cecf8579eb58f1c15430c0 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60950 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4339 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-07Correct file permissions.Idwer Vollering
Some files have incorrect/odd permissions, correct them: remove unnecessary +x flags. Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4490 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-06usbdebug: Hide irrelevent options from menuconfigKyösti Mälkki
No need to show the choice of USB port or controller in case of older hardware where location for usbdebug was hardwired. Change-Id: Ia186bf2c6ed60be2834cf6fd0a1965c8bf81ed4d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4290 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-05lynxpoint: Update LPT-LP PM settingsDuncan Laurie
- updates from 1.6.0 ref code - remove the step comments as they are no longer even close - add constants for LPT revisions build and boot on Falco Check that RCBA+2300[1] is set: > mmio_read32 0xfed1e300 0x00000002 Change-Id: I8b3c5fda3f3170455699a7834239cb991603e7a8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59821 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4326 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05lynxpoint: enable clock gatingAaron Durbin
Implement the LynxPoint BIOS Spec for clock gating. Change-Id: Iaa84cb447bd29b0d13cdda481a1661ea40499de1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59590 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4325 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05lynxpoint: provide gpio_is_native()Aaron Durbin
There's a need to determine if a specific gpio pin is is set up to be a native function or not. Implement this. Change-Id: I91d57a549e0f4fddc0b1849e5f74320fc839642c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59589 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4324 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05lynxpoint: implement additional programming stepsStefan Reinauer
The BIOS spec for LynxPoint calls out additional programming steps for the PCIe Root Ports. Implement those steps from the BIOS spec. These steps are completed before deeper PCIe probing. The "late" programming was removed as that was applicable to Cougar/Panther point where this code was originally copied, though there was some overlap. Change-Id: I64f25e4451e035d98ca6b66b0335bd280b70b074 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59558 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4323 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05lynxpoint: disable pcie devices based on configAaron Durbin
PCIe Root Ports should be disabled based on pin ownership and the strapping configuration. Implement this logic for LynxPoint. The chip_ops->enable_dev() path is no longer used. Instead the PCIe driver handles the enabling and disabling of devices. This allows for having an empty or incomplete device tree since those "allocated" devices do not travel through the chip_ops->enable_dev() path. The coalescing was tested to be working properly, however not all configurations were tested. Change-Id: I1e8bfe5e447b72ff8a4b04b650982d8c1ae0823c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59424 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4322 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05intel/fsp_bd82x6x: Use correct type pointer for mainboard_smi_gpiAlexandru Gagniuc
mainboard_smi_gpi has recently been updated to take a u32 argument from a u16, but the patch introducing the fsp_bd82x6x support has been verified on a master before this change, thus resulting in a 'cast from incompatible type' error. Update the pointer to the correct size argument. Change-Id: I9d62ee43f7c8ed774898f54d29a87cf463b76e91 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4479 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-04Add Intel FSP bd82x6x southbridge supportMarc Jones
Add support for the bd82x6x using the Intel FSP. The FSP is different enough to warrant its own source files for now. The mrc/system agent chromebook solution does much more southbridge initialization and configuration than the FSP version. It may be combined in the future. Change-Id: Ie493945f3d321d854728d231979a0c172d2b36de Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4017 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-03ibexpeak: ensure config compatibility with bd82x6xVladimir Serbinenko
Ibexpeak shares few files with bd82x6x. In order for it to work correctly their config structures from chip.h must match, so include bd82x6x/chip.h in ibexpeak/chip.h Change-Id: Ib56b311b8af04f4e4803d1834724680f604901cd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4277 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-03lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objectsDuncan Laurie
LynxPoint-LP has a lot of GPEs and the "default" set has been moved to register 4 starting at bit offset 96. This means that PME_B0 bit in GPE0_EN/GPE0_STS is now bit 109 in LPT-LP but still bit 13 in LPT-H. suspend on falco and wake from usb 4 | 2013-06-19 10:49:17 | ACPI Enter | S3 5 | 2013-06-19 10:49:22 | ACPI Wake | S3 6 | 2013-06-19 10:49:22 | Wake Source | Internal PME | 0 Change-Id: I443cd4d17796888debed70c0bda27ae09accd09b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59265 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4253 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-12-02global: Fix usage of get_option() to make use of CB_CMOS_ codesAlexandru Gagniuc
Do not directly check the return value of get_option, but instead compare the returned value against a CB_CMOS_ error code, or against CB_SUCCESS. Change-Id: I2fa7761d13ebb5e9b4606076991a43f18ae370ad Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4266 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-02lynxpoint: move all pcie device handling to pcie.cAaron Durbin
Some of the pcie logic was located in pch.c as well as pcie.c. Move all pcie logic to the same pcie.c file. This is a straight cut-and-paste (no logic changes) except for a rename from pch_pcie_enable() -> pch_pcie_enable_dev(). Change-Id: I338c53039b95f255ab9ced313c51193a9d34b404 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59277 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4251 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02lynxpoint: expose pch_disable_devfn()Aaron Durbin
The function to disable devices was formerly named pch_hide_devfn(). This routine was doing more than hiding devices. It was disabling them, i.e. turning them off. Therefore, rename it to pch_disable_devfn(). Also, allow external callers to this function. Change-Id: Id5bb319d4e67892c02a39dff49e45b2811a2f016 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59276 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4250 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02lynxpoint: expose iobp functionsAaron Durbin
The iobp functions are useful to may of the southbridge devices as certain values need to be updated to properly initialize the devices. Therefore expose read, write, and updated iobp functions. Change-Id: Id7fdd8d0d9f022f92d6285ecd8f85a52024ec2bb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59275 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4249 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-01lynxpoint: Do not clear ACPI NVS region on resumeDuncan Laurie
There are useful values in NVS that are set at boot and runtime and they should not be cleared on resume. suspend/resume twice on slippy and ensure that the USB ports are still powered on the second suspend. Change-Id: I4bce60b02b6637f6683120ae9c4a5c64563aacf7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56941 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4210 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-30dmp/vortex86ex: Add timeout for keyboard system flag checking.Andrew Wu
If Vortex86EX PS/2 keyboard controller system flag bit times out, reload controller firmware code and try again. Abort and die after 11 tries as this means the CPU is defect. Also inform the user by printing a message. Change-Id: I24aec4b20d85c721c01e72686f3eb1259f9334b8 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3988 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-11-30ibexpeak: set HAVE_USBDEBUG_OPTIONSVladimir Serbinenko
Previously, I've set this config in mobo config, yet according to Kyösti Mälkki this parameter is southbridge-specific and not mobo-specific. Change-Id: I92428aed5a69d88a371f5d7267bc54ba7530766c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4276 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-11-26lynxpoint: Add an inverted input GPIO typeDuncan Laurie
The wake device input pins are active low and the GPIOs need to be set as inverted when they are marked as an input so they are not spuriously logged. suspend/resume on slippy with trackpad wake: 8 | 2013-05-29 07:43:14 | ACPI Enter | S3 9 | 2013-05-29 07:43:18 | ACPI Wake | S3 10 | 2013-05-29 07:43:18 | Wake Source | GPIO | 12 and with power button wake: 11 | 2013-05-29 07:43:35 | ACPI Enter | S3 12 | 2013-05-29 07:43:40 | EC Event | Power Button 13 | 2013-05-29 07:43:40 | ACPI Wake | S3 14 | 2013-05-29 07:43:40 | Wake Source | Power Button | 0 Change-Id: I15d38dcc9b2fb4b2b0eb27da358fa3c343e22323 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56940 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4209 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-25lynxpoint: Enable USB clock gating, late setup, and sleep prepDuncan Laurie
Both EHCI and XHCI controllers have additional setup steps that are not part of the PEI reference code so they need to be done later. Both controllers also have specific clock gating setup requirements that are now implemented. Additionally they both have specific requirements when entering sleep states. XHCI needs something in S3/S4/S5 and EHCI only has steps for S4/S5 entry. Change-Id: Ic62cbc8b6255455e56b72dd5d52e27a311999330 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57033 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4217 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Add ACPI Method to enable GPIO as wake sourceDuncan Laurie
This is an LPT-LP specific method that will enable a specific GPIO as an ACPI SCI wake source. It can be used by a device _DSW method to enable a pin that is otherwise not configured to generate SCI at runtime. It will set: - GPIO owner to ACPI - GPIO route to SCI - GPIO config to GPIO, Input, Inverted Also clean up and remove ACPI field definitions that are unused and/or incorrect. Change-Id: I14acc2de50e6200f61c2898a7bd1252400e0f0be Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56621 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4189 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-25lynxpoint: Enable extra 16 IOAPIC entries for GPIO PIRQDuncan Laurie
LynxPoint-LP has an additional 16 entries in the IOAPIC that can be assigned to specific GPIOs when they are configured as PIRQ. The maximum redirection entries field in the IOAPIC needs to be set to 0x27 when this is enabled. Additionally specific GPIOs need to be routed to PIRQ so they interrupt via the IOAPIC instead of the GPIO IRQ 14/15. Change-Id: Ie587e1d203422ff6fb7fc5056d20a5ae66720991 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56620 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4203 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: fix mem corruption during ssdt2 genAaron Durbin
The ssdt2 generation code was calling acpigen_patch_len(). However, none of the entries had AML object lengths that needed patching. That resulted in the following message: ASSERTION FAILED: file 'src/arch/x86/boot/acpigen.c',  line 52 Additionally, this caused an errant write to a memory address whose value was in the variable ltop. This was the 0 address. Change-Id: I44abf5a4e4225220575aee6b5c9bb6b0be093a28 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56299 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4182 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Fix XHCI controller device in ACPIDuncan Laurie
The ACPI code was defining two EHCI controllers and ignoring the XHCI controller. This changes the second EHCI controller to be XHCI instead and changes the wake resource to indicate S3 and not S4. cat /proc/acpi/wakeup Device S-state Status Sysfs node HDEF S4 *disabled pci:0000:00:1b.0 EHCI S3 *enabled pci:0000:00:1d.0 XHCI S3 *enabled pci:0000:00:14.0 Change-Id: If28775e6ef8608c22c85ca91d91d1f598ec7755d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56263 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4181 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Enable SerialIO clock in PCI modeDuncan Laurie
The clock gating register at offset 0x800 is managed by the clock driver in the kernel when the devices are in ACPI mode. When in PCI mode we should force enable the clock here. When in ACPI mode or the device is disabled it should be put in D3Hot state. > i2cdetect -y -r 10 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- Change-Id: Ib93ffd41bf36386d5ce63bfc0ae6597f3e23bc48 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56122 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4180 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25slippy: Enable EC SMIDuncan Laurie
Enable GPIO SMI for GPIO34 and set it as inverted so it is only generated when it is raised by the EC. 1) ec console command: lidopen 2) wait until booted to developer screen 3) ec console command: lidclose 4) ensure system turns off Change-Id: I7d50f171f3f4539c7c264103d1ffc7c5d0f1c7ba Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56052 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4177 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-25lynxpoint: update azalia device idsAaron Durbin
The vendor ids were never updated to reflect LynxPoint's device ids. Therefore, none of the initialization was being ran. Fix this. Change-Id: Ic6ec00c9fb1cbcb6087fd89b0acff3d83294ac6a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/55821 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4173 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Change SerialIO device enable reporting to ACPIDuncan Laurie
In order to report whether coreboot enabled a SerialIO device in ACPI mode we had been relying on reading NVS in the _STA method for the SerialIO device. The ACPI _STA method has restrictions on what it can access and is unable to access OperationRegions outside its scope which means it should not be trying to read NVS. This change adds a new SSDT to the ACPI tables and fills it with constants that indicate whether or not a device is enabled in ACPI mode. The ACPI code is changed to read these variables from the SSDT and use that instead of trying to query a variable in NVS. Attempt to use lpt-clk driver to probe the device clocks for SerialIO devices and see that the kernel does not complain about accessing the GNVS region. Change-Id: I8538bee4390daed4ecca679496ab0cb313f174ce Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51369 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4170 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25slippy: Minor vboot related fixesDuncan Laurie
- Disable EC software sync for now - Report correct EC active firmware mode - Force enable developer mode by default - Set up PCH generic decode regions in romstage - Pass the oprom_is_loaded flag into vboot handoff data Change-Id: Ib7ab35e6897c19455cbeecba88160ae830ea7984 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51155 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4169 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Expose ACPI Device for LP GPIO controllerDuncan Laurie
In order to probe the gpio-lynxpoint kernel driver the LP GPIO controller needs to be exposed as a specific ACPI device. This also allows the resources to be exposed to the OS via this device instead of the catch-all LPC device. Ensure the driver loads at boot: gpiochip_find_base: found new base at 162 gpiochip_add: registered GPIOs 162 to 255 on device: INT33C7:00 Also ensure the driver is visible in sysfs: $ cat /sys/devices/platform/INT33C7:00/gpio/gpiochip162/label INT33C7:00 Change-Id: I9f79c008f88da9b67ed1cdfdb9d3a581ce8f05ff Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50215 Reviewed-on: http://review.coreboot.org/4158 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Move ME lock down to ramstageDuncan Laurie
Now that we have RW ramstage we don't need to have the management engine lock down step done in a final SMM. ME: mkhi_end_of_post ME: END OF POST message successful (0) PCI: 00:16.0: Disabling device Change-Id: I9db4e72e38be58cc875c1622a966d8fcacc83280 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49757 Reviewed-on: http://review.coreboot.org/4153 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Add missing ME MBP entriesDuncan Laurie
There were two undefined MBP types that are now defined. These include NFC status and some interesting timing data. ME: Wake Event to ME Reset: 6 ms ME: ME Reset to Platform Reset: 7 ms ME: Platform Reset to CPU Reset: 51 ms Change-Id: I67bf1f303f3c32497041e64c40eb9ccb6a63d88a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49756 Reviewed-on: http://review.coreboot.org/4152 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: export mem console pointer in ACPIAaron Durbin
Instead of having an OS re-parse cbmem book-keeping records for the cbmem allocator just to get the console buffer export the pointer to the memory console directly in a field named 'CBMC'. This field lives in the GNVS table. Change-Id: Ief0c4da7b18df66feb9c816c9f4abdf5a72bd3a4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49764 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4149 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Updates to power management and clock gatingDuncan Laurie
Slight tweaks found when looking at latest ref code when investigating package C-state issues. A few bits in the clock gating register don't match the documentation and are also cleaned up. Change-Id: I36ced7280c160b114c70b2eeafc8b24813ff2f6a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49330 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4142 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25Support for Ibexpeak southbridgeVladimir Serbinenko
Part of X201 port. Change-Id: If17d707004aba9f08459dbd8f3a146fa3c076aa9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4052 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-11-24haswell: Configure PCH power sharing for ULTDuncan Laurie
This reads PCH power levels via PCODE mailbox and writes the values into the PMSYNC registers as indicated in the BWG. Change-Id: Iddcdef9b7deb6365f874f629599d1f7376c9a190 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49329 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4143 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24lynxpoint: Add a function to set an individual GPIODuncan Laurie
This will be used in a later commit to do some specific power sequencing. Change-Id: Id7f033bb80aed915c2498ea910cb3ac7290da37f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48947 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4137 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24lynxpoint: Rework LP GPIO handlingDuncan Laurie
This adds some macros for the common GPIO defines and drops the gpio number definition from each entry. The end result is much easier to read. The wtm2 mainboard gpio list is modified to use this. Also fix a bug in the LP version of get_gpio() that was always returning zero due to a miscompare. Change-Id: I143e5aee412af1eda84e35f8026f31cf13df508e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48946 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4138 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24smi: Update mainboard_smi_gpi() to have 32bit argumentDuncan Laurie
With the LynxPoint chipset there are more than 16 possible GPIOs that can trigger an SMI so we need a mainboard handler that can support this. There are only a handful of users of this function so just change them all to use the new prototype. Change-Id: I3d96da0397d6584f713fcf6003054b25c1c92939 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49530 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4145 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24slippy: Prepare LPC IO decode ranges for ECDuncan Laurie
- 0x200-0x208 for host command window - 0x800-0x8ff for host command arguments and parameters - 0x900-0x9ff for exported EC memory map Change-Id: I064b969843ef0d3c602793d1cb3d82715775c05e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49755 Reviewed-on: http://review.coreboot.org/4151 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24dmp/vortex86ex: Move DMP specific POST code defines into one fileAndrew Wu
Move into src/cpu/dmp/dmp_post_code.h Change-Id: If9f4d842f352eb41618e71f49a226d3cc4ad0b46 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3989 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-12AMD Hudson: Move function s3_resume_init_data to southbridgeZheng Bao
Besides the AGESA static settings, the settings in mainboard/buildOpt.c also change the final configuration. We need to make sure the settings in FchParam in resume stage are the same as they were in cold boot stage, otherwise the board can not wake up more than once. Tested on AMD/Olive Hill, AMD/Parmer and ASRock/imb-a180. (USB keyboard doesn't work when board wakes up. It is not introduced by this patch. It needs more debugging.) Change-Id: I5a5e5502080e358ffc3577dc6a40bb762844d998 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/3932 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2013-11-05southbridge/via/vt8237r/ctrl.c: Remove set but unused variable `regm3`Paul Menzel
Change-Id: I6bb652419a54b7b7190e417346581f38335425ae Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3985 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-30southbridge/intel/i82801ix/lpc.c: Remove unused variable `dummy`Paul Menzel
Removing `-Wno-unused-but-set-variable` from `CFLAGS` the build for QEMU Q35 and Roda RK9, both using the Intel 82801Ix southbridge, fail with the following error. src/southbridge/intel/i82801ix/lpc.c: In function 'i82801ix_enable_apic': src/southbridge/intel/i82801ix/lpc.c:45:5: error: variable 'dummy' set but not used [-Werror=unused-but-set-variable] cc1: all warnings being treated as errors Removing `dummy` should be safe as GCC probably optimizes it away before anyway. That no dummy variable is used for an RCBA [1] access in Intel Lynx Point supports that this can be dropped safely. [1] root complex base address [2] src/southbridge/intel/lynxpoint/early_pch.c Change-Id: I1c138a3498228dbd025f68d5e6af0acc29ed3460 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3982 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-22vortex86ex: Defer checking PS/2 keyboard controller system flagAndrew Wu
Don't check keyboard controller system flag until before calling pc_keyboard_init(). This makes waiting time shorter. Change-Id: I2cdb533a5b25575e1717434533a60decf748f6d8 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3958 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-22usbdebug: Fix boards without EARLY_CBMEM_INITKyösti Mälkki
The main usbdebug file lib/usbdebug.c was removed from romstage build with commit f8bf5a10 but the chipset-specific parts were not, leading to unresolved symbol errors for AMD platforms. Add a silent Kconfig variable USBDEBUG_IN_ROMSTAGE for convenient use of this feature. Change-Id: I0cd3fccf2612cf08497aa5c3750c89bf43ff69be Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3983 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15intel/i82371: Remove HAVE_ACPI_RESUMEKyösti Mälkki
This is needed to apply a rule that get_top_of_ram() in romstage is required to select HAVE_ACPI_RESUME, otherwise chipset/board has no means to backup low memory to CBMEM on s3 resume. Only board affected is asus/p2b. Change-Id: Ia5cbf4e5e40af25f52a19de584d8bc5370487154 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3971 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-14ck804: hide IOAPIC base address in PCI_BASE_ADDRESS_1Jonathan A. Kollasch
Linux unhelpfully "fixes" the value in PCI_BASE_ADDRESS_1 when it is 0xfec00000 (that is, outside the range of bus 0 address space). This causes IOAPIC interrupts to fail to work under Linux. This issue was originally unnoticed by me when testing as sanity checking such as this is not done by NetBSD. Hiding the IOAPIC BAR is done by the OEM BIOS on the ck804 boards I've checked. Change-Id: I736db163750f709d68c988fac075597a50b29ab7 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/3963 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-14ck804: obtain stored IOAPIC address from allocator instead of registerJonathan A. Kollasch
Change-Id: Ibdd438455a545aa9266b0fd893d5ff27124ab22c Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/3961 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-13dmp/vortex86ex: Initialize PS/2 keyboard.Andrew Wu
Call pc_keyboard_init function in southbridge. It makes PS/2 keyboard work in coreinfo payload. Change-Id: Idb79f87b09eeeade94e966fb8769dec7578e2cf5 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3957 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-13ck804 lpc: use PCI_BASE_ADDRESS_1 instead of 0x14Jonathan A. Kollasch
Change-Id: I752a4a890e1f610651a2c688cf42350ce8e9deaa Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/3962 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-10-01qemu: q35: avoid address conflictGerd Hoffmann
Qemu has the fw_cfg interface at 0x510, which conflicts with power management base address in coreboot. Move the pmbase to a non-conflicting address. No need to worry about speedstep, it is not supported by qemu and isn't enabled in the qemu config. Change-Id: I3e87d8301988028ca0ea7d96c08b4e26ac15a7c2 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3938 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-25usbdebug AMD: Add choice of EHCI controllerKyösti Mälkki
Chipsets sb700 and sb800/hudson have more than one USB EHCI controller, implement the selection logic using already existing Kconfig option. Change-Id: I9e0df1669d73863c95c36a3a7fee40d58f6f097e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3928 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-24southbridge/cimx/sb900: Rename headers to match sb700 & sb800Corey Osgood
Northbridge code includes these headers, so they all need to have the same name to allow different combinations of northbridge and southbridge. This changes the sb900 names to match sb700 & sb800, and points agesa/family12 and amd/torpedo to the new file names. Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Reviewed-on: http://review.coreboot.org/3825 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-09-21timestamps intel: Move timestamp scratchpad to chipsetKyösti Mälkki
This retrieves back the value stored with store_initial_timestamp() in the bootblock for southbridge. Change-Id: I377c823706c33ed65af023d20d2e4323edd31199 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3908 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-17Fix whitespace leaked into treeKyösti Mälkki
Clean whitespace errors that have gotten past lint-stable-003-whitespace and gerrit review. Change-Id: Id76fc68e9d32d1b2b672d519b75cdc80cc4f1ad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3920 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-11CBMEM: Backup top_of_ram instead of cbmem_tocKyösti Mälkki
AMD northbridges have a complex way to resolve top_of_ram. Once it is resolved, it is stored in NVRAM to be used on resume. TODO: Redesign these get_top_of_ram() functions from scratch. Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3557 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-10intel/i945 intel/i82801gx: remove explicit pcie config accessesKyösti Mälkki
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: I46e69154cf576ddb642c34b6dd2bc0d27cc19b7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3811 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-10intel/i82801ix: remove explicit pcie config accessesKyösti Mälkki
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: Ie6776b04ca0ddb89a0843c947f358db267ac4a70 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3809 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-09-06usbdebug: Fixes for LynxPoint LPKyösti Mälkki
Keep the EHCI BAR unchanged to keep usbdebug working. Change-Id: I7fe0eed24a66cb5058b49ee3fc0350d91089ed7a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3477 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29intel usbdebug: Add choice of EHCI controllerKyösti Mälkki
Add option to choose one of the EHCI controllers in recent intel chipsets for usbdebug use. Since EHCI controller function changes from 0:1d.7 to 0:1d.0 in rcba_config() for some mainboards, check the PCI class code for match. Change-Id: I18a78bf875427c163c857c6f0888935c1d2a58d4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3440 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29usbdebug: Support choice of EHCI controllerKyösti Mälkki
Nowadays, chipsets or boards do not only have one USB port with the capabilities of a debug port but several ones. Some of these ports are easier accessible than others, so making them configurable is also necessary. This change adds infrastructure to switch between EHCI controllers, but does not implement it for any chipset. Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3438 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29usbdebug: Change debug port scanningKyösti Mälkki
On AMD platforms, setting of USBDEBUG_DEFAULT_PORT=0 tries to scan all physical ports one after other in incrementing order. To avoid possible problems with other USB devices, one can select the port number here and bypass the scan. Intel platforms can communicate with usbdebug dongle on one physical port only, and this option makes no difference there. Change-Id: I45be6cc3aa91b74650eda2d444c9fcad39d58897 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3872 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-27AMD f16kb: use AZ_PIN in Kconfig to customize AZALIA_PIN in YangtzeWANG Siyuan
src/southbridge/amd/agesa/hudson/Kconfig config default value, mainboard Kconfig config value for specific mainboard. bit 1,0 - pin 0 bit 3,2 - pin 1 bit 5,4 - pin 2 bit 7,6 - pin 3 Change-Id: I54a87cf734685515a3e1850838ca7d94387172ce Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3879 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-08-24usbdebug: Change reference to EHCI BARKyösti Mälkki
Change the defines, as follow-up patch will replace use of constant CONFIG_EHCI_BAR. Change-Id: I44ff77cb7a2826f3b43d8d46440fd4482a29d18c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3875 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-24Add pci_devfn_t and use with __SIMPLE_DEVICE__Kyösti Mälkki
Declare the functions that may be used in both romstage and ramstage with simple device model. This will later allow to define PCI access functions for ramstage using the inlined functions from romstage. Change-Id: I32ff622883ceee4628e6b1b01023b970e379113f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3508 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-23usbdebug: Do not support logging from SMMKyösti Mälkki
Letting SMI handler touch EHCI controller is an excellent source of USB problems. Remove usbdebug entirely from SMM. It may be possible to make usbdebug console work from SMM after hard work and coordination with payloads and even OS drivers. But we are not there. Change-Id: Id50586758ee06e8d76e682dc6f64f756ab5b79f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3858 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-08-16Correct spelling of shadow, setting and memoryPaul Menzel
Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3768 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-16AMD Southbridge CS5536: make use of #include <device/smbus_def.h>Christian Gmeiner
Change-Id: Ia2dff49d3e2b086546785d992f2d92bcf4d1ef1c Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3376 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15AMD Fam16: Add OSC method to PCI0Mike Loptien
The _OSC method is used to tell the OS what capabilities it can take control over from the firmware. This method is described in chapter 6.2.9 of the ACPI spec v3.0. The method takes 4 inputs (UUID, Rev ID, Input Count, and Capabilities Buffer) and returns a Capabilites Buffer the same size as the input Buffer. This Buffer is generally 3 Dwords long consisting of an Errors Dword, a Supported Capabilities Dword, and a Control Dword. The OS will request control of certain capabilities and the firmware must grant or deny control of those features. We do not want to have control over anything so let the OS control as much as it can. The _OSC method is required for PCIe devices. During Linux boot, an error is logged to dmesg if _OSC is not found. Change-Id: Icf6e7a82284d03d23fd30ee7b7db17754e988c9a Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3823 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-08-15AMD Fam16: Add secondary bus number to CRES methodMike Loptien
Adding the 'WordBusNumber' macro to the PCI0 CRES ResourceTemplate in the AMD FCH ACPI code. This sets up the bus number for the PCI0 device and the secondary bus number in the CRS method. This change came in response to a 'dmesg' error which states: '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS' By adding the 'WordBusNumber' macro, ACPI can set up a valid range for the PCIe downstream busses, thereby relieving the Linux kernel from "guessing" the valid range based off _BBN or assuming [0-0xFF]. The Linux kernel code that checks this bus range is in `drivers/acpi/pci_root.c`. PCI busses can have up to 256 secondary busses connected to them via a PCI-PCI bridge. However, these busses do not have to be sequentially numbered, so leaving out a section of the range (eg. allowing [0-0x7F]) will unnecessarily restrict the downstream busses. Change-Id: Ib2d36f69a26b715798ef1ea17deb0905fa0cad87 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3822 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 08:02:28 +0000