Age | Commit message (Collapse) | Author |
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Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Note: enable AHCI in seabios and apply seabios patch:
http://www.mail-archive.com/seabios@seabios.org/msg00437.html
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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and remove RS780 get_cpu_rev().
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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some platform only use sb800 cimx code, not use AGESA v5 code.
for such platform, one can compile the sb800 cimx and AGESA v5 lib code.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Those settings should be handled by the generic PCI/Cardbus code,
and not by the driver itself.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6515 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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to unify calls to *_enable_usbdebug()
* rename *_enable_usbdebug() to enable_usbdebug()
* move enable_usbdebug() to generic romstage console init code
and drop it from the individual romstage.c files.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6495 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This fixes 4GB memory issues.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Kerry she <kerry.she@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html
It's about time we follow this advice.
Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and
drop unused CPP define
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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There's an off-by-one error in the ACPI GP_LVL declaration:
it declares GL00 with a bit count of 6, and continues with GP07
afterwards. This should be GP06, as the first bitfield covers
GP00-GP05.
While at it, change it to GP00-GP05, as right now GL00 isn't used,
and single bitfield are more usable here.
Also adjust the Getac P470, as this is the only user of those defintions
right now.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Since the SB700 has changed to sb7xx_51xx, change legacy name in
other mainboard.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Bit 0 of pm reg#74 have to be set turn on system after power resumes.
See '42661_sb600_rrg_nda_3.02.pdf' (or '46155_sb600_rrg_pub_3.03.pdf')
for details, look for 'PwrFailShadow'.
[Patrick: I didn't include the get_options reorganization as get_option
doesn't overwrite "on" if power_on_after_fail isn't found in CMOS.
Style changes were also left out.]
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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all boards to the new config scheme.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons.
Also it enables the FID/VID changes in SB. Jakllsch had some troubles with that too but on am2 CPU. Those bits are only documented in SB600. They arent in RRG RPR and BDG.
Signed-off-by: Rudolf Marek <r.marek@asssembler.cz>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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coreboot used to set the chipset to IDE mode unconditionally.
Now, the user has a couple of ways to choose the configuration:
- If a CMOS variable sata_mode exist, it is used to decide if IDE or
AHCI is to be used as interface.
- If not, a Kconfig option is used.
- If unchanged, the Kconfig option is set to IDE.
So unless the cmos.layout is extended or Kconfig is modified, this won't
change behaviour.
[Patrick: Compared to Josef's version, I changed the Kconfig option to
be boolean, instead of a magic string. Also, the "IDE" default is
handled in Kconfig, instead of an additional line of code.]
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The K8T800 is almost identical to the K8T800Pro, also added to this patch.
The K8T800_OLD is also defined, which is an older version of the K8T800,
but which has no driver and early HT code yet. Also extended the K8M890 VGA
driver to work for the K8M800 (not tested). According to the datasheet, the
K8T890 and K8T800 are similar enough to be able to use the same
initialization code. At least for the K8T800, this is sufficient to have
a working HT link with the CPU, and to initialise the V-Link to the
southbridge.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Setting bit#21 in k8_f0#68 is part of the errata#169
which is handled in amdk8/coherent.c
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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is dependent on the AMD CIMx/SB800 code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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only Serial/SIO/RTC.
Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only...
Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc...
Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad.
Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded.
While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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If enabled, set up 0xe0000000..0xf0000000 as MMCONF
area. Must still be configured in per-board ACPI for
the OS to pick it up, so it's disabled by default.
Signed-off-by: Josef Kellermann<seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Some RS690 devices require subvendor/subdevice IDs to
be programmed at locations other than default 0x2c.
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This is so that boards can determine them on runtime based on hardware
properties, if so desired.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Joseph Kellermann <Joseph.Kellermann@heitec.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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already used the new order)
This is in reponse to feedback that the original setup was too complicated.
New cbfs-files-y behaviour:
cbfs-files-y contains the names of files as they appear in CBFS. The
arguments describe the on-filesystem name, the type and (optionally) the
position. Example:
cbfs-files-y += foo
foo-file := bar
foo-type := splashscreen
foo-position := 0xffff8000
This configures a CBFS file called "foo" that is marked "splashscreen",
located at 0xffff8000 in flash and contains the data of the file "bar"
in the filesystem (either in the current directory, ie. where the
corresponding Makefile.inc resides, or if that doesn't exist, relative
to the toplevel directory).
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Serial/SIO/RTC. Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only...
Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc...
Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad.
Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded.
While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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As Rudolf called.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The AcpiPmaCntBlk have to be set.
Further research is needed to find out why.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Note:
1. bimini_fam10/Kconfig: Set GENERATE_MP_TABLE in Kconfig. This will make sure the
smp_write_config_table will run. Then intr_data will be written
into 0xC00/0xC01.
2. bootblock: Use PCI_DEV(0, 0x14, 3) instead of
pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_LPC), 0).
The pci_locate_device will cause the system crash.
3. fadt.c: Change fadt revision to 1. 3 will cause the linux hang. Why?
4. early_setup.c: pmio 0x65 has change its meaning.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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by using 'Int32FromChar' macro, instead of the ASCII code.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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We did the same with other chipsets in r6150.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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and fix CIS mode comments.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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to FG (FooGlue). As the GX2 has no VIP port.
-Change the Memmory setup MSR register names so they correspond better to the
databook. (Part1)
This is less confusing for beginners.
-Add a MSR printing function to northbridge.c like in the Geode LX code.
-Remove the AES register names.(GX2 has no AES registers)
-Delete some unused code.
-Clean up GX2 northbridge code to match Geode LX code.
-Add missing copyright header to northbridge.c.
-Move hardcoded IRQ defining from northbridge.c to irq_tables.c .
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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-Remove some white spaces.
-Remove some leading zeros.
-Fix a typo in LX code.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- nokia/ip530/devicetree.cb, southbridge/ti/pci1x2x/pci1x2x.c:
- Fix SMSC FDC37B787 name (was a typo).
- Disable PS/2 keyboard/mouse LDN, the IP530 doesn't have either.
- Fix typo: s/PCI_DEVICE_ID_TI_1420/PCI_DEVICE_ID_TI_1520/.
- All of these are confirmed by Marc Bertens on IRC.
- Fix a few CHIP_NAME HP board names.
- Random whitespace and coding-style fixes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Don't include cmc.bin to the build. It's required, but we don't ship it
- mptable's API changes a bit. Adapt.
- Fix ACPI for new iasl versions with improved code validation
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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which uses it.
Compiles, but not boot tested lately.
Many things missing (eg. SMM support, proper ACPI, ...)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6178 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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the get_cbmem_toc because macro magic did not work well.
The writes to NVRAM are not used in asrock board (k8 pre rev f) but they should work when used with am2 boards. In fact maybe the suspend will work on mahogany or others ;) - with some simple patch which follows for asrock.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6173 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6166 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Factor out the ROM decode enable functionality into bootblock.c and
handle it via the usual TINY_BOOTBLOCK mechanism.
Use "select TINY_BOOTBLOCK" in the southbridge, not individual boards.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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All southbridges using TINY_BOOTBLOCK have a bootblock.c files which
simply includes an enable_rom.c files. As discussed on the mailing
list, drop the enable_rom.c file by merging it into bootblock.c.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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> Definitively a iasl problem, it can't even disassemble it's own
> output back to something equivalent to the input file.
> It seems to be generating Bytecode for the Add where it shouldn't.
Here is a solution using the SSDT.
Unfortunately iasl does not resolve simple arithmetic at compile
time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the
Processor statement.
This patch instead dynamically generates the processor statement.
I can't use the speedstep generate_cpu_entries() directly since the
cpu doesn't support speedstep.
For now the code is in the southbridge directory, but maybe it
should go into cpu/intel/ somewhere.
IIRC notebook cpus of the era can already have speedstep, so it
would probably be possible to pair the i82371eb with a
speedstep-capable cpu...
Also, I don't know if multiprocessor boards (abit bp6?) would need
to be handled differently.
Abuild-tested.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.
Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)
- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong
Signed-off-by: <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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De-asserts STRAP_BIF_all_valid for
PCIE-GFX core.
After lane reversal,
Asserts STRAP_BIF_all_valid for
PCIE-GFX core.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: QingPei Wang <wangqingpei@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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> Stefan Reinauer wrote:
> > The specified IO port is most likely wrong. As the comment mentions, the
> > SSDT is a good place for that. A preprocessor define used both in the
> > CPU init code and in the asl would solve the problem without an SSDT.
> > For some info on CPU SSDT creation on intel check out
> > src/cpu/intel/speedstep/acpi.c
>
> The IO port is ok (and I wrote the comment myself ;)):
> DEFAULT_PMBASE is 0xe400
> PCNTRL reg offset is 0x10
>
> Using the preprocessor will probably work too if iasl can do simple
> arithmetic (likely yes), I'll look into that.
BTW, my first idea was to use an acpi method that looks up pmbase in
the pci cfg space, but when I define a method like this:
Method(TEST, 2)
{
Return (Add(Arg0, Arg1))
}
I get:
|build/mainboard/asus/p2b/dsdt.ramstage.asl 9: Processor (CPU0,
|0x01, TEST(0xe400, 0x10), 0x06) {}
|Error 4096 - syntax error, unexpected PARSEOP_NAMESEG,
|expecting ')' ^
While using the builtin Add() directly works.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6130 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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I cleaned up the patch and moved most of the dsdt.dsl and
acpi_tables.c into the southbrige/northbridge directory.
Updated patch should fix abuild error and incorporates suggestions
on irc by uwe (thanks for the comments).
Thanks to Idwer Vollering <vidwer@gmail.com> for the original patch.
Tested:
Linux (poweroff, powerbutton event)
XP (poweroff, powerbutton event)
Abuild-tested
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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In bcm5785_enable_rom(): Use PCI IDs from pci_ids.h instead of hardcoding,
and use 'dev' instead of 'addr' as device_t variable name.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6125 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Also, add missing license header to amd8111_enable_rom.c, add some more code
comments and use PCI IDs from pci_ids.h instead of hardcoding.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Also, move CONFIG_HT_CHAIN_END_UNITID_BASE #ifdef block to mcp55.h to make
the build work (but this is a good idea anyway, as it's used in
multiple files).
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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initialized properly because the pcie link takes some time to come
up.
I set the timeout rather arbitrary to 100ms, this is what a BIOS_ERR
and higher only boot looks like on my system (with pcie printks set
to BIOS_ERR so they show up):
|Device error
|Device error
|PCI: 00:02.0 PCIe link up after 35800 us
|PCI: 00:03.0 PCIe link up after 12900 us
|PCI: 00:03.1 PCIe link timeout
|PCI: 00:03.2 PCIe link up after 32000 us
|APIC: 00 missing read_resources
|I2C: 01:50 missing read_resources
|I2C: 01:51 missing read_resources
|I2C: 01:52 missing read_resources
|I2C: 01:53 missing read_resources
|Start bios (version pre-0.6.2-20101025_023503-nukunuku)
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6121 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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AMD RS780 uma graphics. Tested with frame buffer sizes 64m through 1GB
by running dxdiag and Windows media player at 1600x1200 true color.
Additional changes needed to boot Win7 on Mahogany_fam10 will follow.
-- Enable and program the debug bar as required by the ATI graphics driver.
First, make the debug bar writable and allow resource allocation code
to program it. Once programmed, enable its operation.
-- Disable the family 10h processor mmconf while the RS780 mmconf is in use.
-- Make strap programming more closely follow the reference BIOS.
-- Disable PCIe bar 3 after using it.
-- UMA size is no longer hardcoded.
-- Disable write combining for all steppings to eliminate stability problem.
-- Correct task file data.
-- Improve the accuracy of the Atom table that passes information to the driver.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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CONFIG_HAVE_ACPI_RESUME == 1 getting rid of ugly define in romstage.c
2) the patch implements get_cbmem_toc in chipset specific way if defined.
On Intel targets it should be unchanged. On K8T890 the the cbmem_toc is read from NVRAM. Why you ask? Because we cannot do it as on intel, because the framebuffer might be there making it hard to look for it in memory (and remember we need it so early that everying is uncached)
3) The patch removes hardcoded limits for suspend/resume save area (it was 1MB) on intel. Now it computes right numbers itself.
4) it impelements saving the memory during CAR to reserved range in sane way. First the sysinfo area (CAR data) is copied, then the rest after car is disabled (cached copy is used). I changed bit also the the copy of CAR area is now done uncached for target which I feel is more right.
I think I did not change the Intel suspend/resume behaviour but best would be if someone can test it. Please note this patch was unfinished on my drive since ages and it would be very nice to get it in to prevent bit rotten it again.
Now I feel it is done good way and should not break anything. I did a test with abuild and it seems fine.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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initializing VGA happens pretty much as the last thing before starting the
payload. Hence, drop VGA console support, as we did in coreboot v3.
- Drop VGA and BTEXT console support.
Console is meant to be debugging only, and by the time graphics comes up
99% of the risky stuff has already happened. Note: This patch does not remove
hardware init but only the actual output functionality.
The ragexl driver needs some extra love, but that's for another day
- factor out die() and post()
- drop some leftover RAMBASE < 0x100000 checks.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: QingPei Wang<wangqingpei@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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