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2013-06-13Revert "Add support for Intel Ibex Peak (Mobile 5) southbridge"Stefan Reinauer
This reverts commit 0210119b4b95e84f954cfd6dc11aafbc187421af Change-Id: I5be3f2a54394c592650a0dcd671e4a72ae796cb2 Reviewed-on: http://review.coreboot.org/3443 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-12Add support for Intel Ibex Peak (Mobile 5) southbridgeStefan Reinauer
Change-Id: If56f2cacc5f1b2ef9c7b6aea508d458a43dd1309 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3397 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12usbdebug: Drop printk within console_init()Kyösti Mälkki
In case with EARLY_CONSOLE, this printk is called before any other console is configured to transmit data. This outputs garbage on CONSOLE_SERIAL as baudrate is not yet programmed. For case without EARLY_CONSOLE, the order in which different console drivers initialize is obscure. Might sometimes work properly. Change-Id: I3792161e0a6dc17e17262048cc9136044dd69dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3384 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-12Fix i82801a/b/c/d IOAPICKyösti Mälkki
Setting IRQ delivery to FSB got lost in the rebase process for commit e6143531. I captured following error on dmesg and this patch fixes it for i82801dx. ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 ..MP-BIOS bug: 8254 timer not connected to IO-APIC ...trying to set up timer (IRQ0) through the 8259A ... ..... (found apic 0 pin 2) ... ....... failed. ...trying to set up timer as Virtual Wire IRQ... ..... works. Change-Id: I0768976cc6b0deab213ad9bd4771e0f278de634c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3371 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-12intel/*/smi.c: Output correct GPIO in ALT_GP_SMI_STS register dumpKonstantin Aladyshev
Mapping is as follows: bit 15 corresponds to GPIO15 ... bit 0 corresponds to GPIO0. Change-Id: I661ce56d9373887270ba3c0518892fbbe6d9de7c Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/3436 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11intel/bd82x6x/Makefile.inc: Revert duplicate addition of `usb_debug.c`Paul Menzel
Currently in Intel BD82x6x southbridge’s `Makefile.inc` the file `usb_debug.c` is added twice to the build. This was introduced in commit 4063ede3fb571110c3e65c321049cc2687cc54fa Author: Ronald G. Minnich <rminnich@google.com> Date: Mon Feb 4 20:31:51 2013 -0800 bd82x6x: Fix compiling with USB debug port support Reviewed-on: http://review.coreboot.org/2784 but was unneeded because it had been already added in the following commit. commit 4141993536039e0d45caeacb745a89d388f0724b Author: Sven Schnelle <svens@stackframe.org> Date: Sat Jul 28 08:52:44 2012 +0200 bd82x6x: Fix CONFIG_USBDEBUG Reviewed-on: http://review.coreboot.org/1376 Therefore basically revert that hunk. There is no policy on how to order these additions, so leave it to a possible separate commit, unifying this. Kyösti Mälkki suspects that these additions were meant for the Intel Lynx Point [1]. [1] http://review.coreboot.org/#/c/3424/ Change-Id: Iaa8de6fcc0d6f3a0a92a28fcb603d7777aa8b24c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3425 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11Fix cycle error in intel southbridges to display GPI statusKonstantin Aladyshev
Fix obvious mistake in cycle that displays GPI status I hope i found all duplicates of it. Change-Id: Ic21ff3ecab85953463e5c23daf808dd5edc82ff8 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/3435 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-10early_smbus: Add early SMBus implementation for VIA chipsetsAlexandru Gagniuc
Add a common implementation of SMBus functionality for early chipsets. Note however, that existing via chipsets are not ported to this code. Porting will require hardware testing to make sure everything is fine. This code is used in the VIA VX900 branch. Change-Id: If5ad8cd0942ac02d358a0139967e7d85d395660f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/144 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-06intel/bd82x6x: Add option to include ethernet firmwareNico Huber
Change-Id: Idf804ed29a67bad732df19e6981f74c8d0c354b5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3388 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06intel/bd82x6x: fix building usb debug on SNB/IVBPatrick Georgi
Change-Id: Ica3afbf8277cb025251da7af181f8de0d0036b45 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3389 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-03AMD Geode CS5536: downgrade BIOS_ERRChristian Gmeiner
There is no need to use everywhere BIOS_ERR. Change-Id: If33d72919109244a7c3bd96674a4e386c8d1a19e Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3307 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Denis Carikli <GNUtoo@no-log.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-03Intel Lynx Point: LPC: Unify I/O APIC setupPaul Menzel
Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Define `ACPI_EN` in the header file `pch.h`. As commented by Aaron Durbin, a separate `pch_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3182 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-06-03Intel BD82x6x: LPC: Unify I/O APIC setupPaul Menzel
Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Define `ACPI_EN` in the header file `pch.h`. As commented by Aaron Durbin, a separate `pch_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3183 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-05-20AMD AGESA Hudson: Include `stdint.h` and `io.h` to fix buildPaul Menzel
Apparently the files `smbus.{h,c}`, where never used and therefore build beforehand. Needing one function in them for the ASUS F2A85-M the build fails as some headers are missing. Including the headers `stdint.h` and `io.h` fixes the following errors. […] CC southbridge/amd/agesa/hudson/smbus.romstage.o In file included from src/southbridge/amd/agesa/hudson/smbus.c:23:0: src/southbridge/amd/agesa/hudson/smbus.h:67:24: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:67:43: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:67:55: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:68:25: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:68:44: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:68:56: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:68:69: error: unknown type name 'u8' src/southbridge/amd/agesa/hudson/smbus.h:69:24: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:69:43: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:70:24: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:70:43: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:70:55: error: unknown type name 'u8' src/southbridge/amd/agesa/hudson/smbus.h:71:20: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:71:35: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:71:49: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:71:59: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:71:69: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:72:20: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:72:35: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:72:49: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:72:59: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:73:20: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:73:32: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:73:44: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:73:54: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.c: In function 'smbus_delay': src/southbridge/amd/agesa/hudson/smbus.c:27:2: error: implicit declaration of function 'outb' [-Werror=implicit-function-declaration] src/southbridge/amd/agesa/hudson/smbus.c:27:2: error: implicit declaration of function 'inb' [-Werror=implicit-function-declaration] […] Probably all the (AMD(?)) `smbus.{h,c}` suffer from this and should be fixed. Even better, as these function do not differ between most boards, the file should be moved out from the specific southbridge directories. [1] http://qa.coreboot.org/job/coreboot-gerrit/6168/testReport/junit/(root)/board/i386_asus_f2a85_m/ Change-Id: I285101fa06a365da44fa27b688c536e614d57f50 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3202 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-05-20ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt casePaul Menzel
Currently the code in the if statement if (!byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); only gets executed if `byte == 0x0`, that means only in the default case where RAM voltage is 1.5 Volts. But the RAM voltage should be changed when configured for the non-default case. So negate the predicate to alter the RAM voltage for the non-default cases. To prevent the build error OBJCOPY cbfs/fallback/coreboot_ram.elf coreboot-builds/asus_f2a85-m/generated/crt0.romstage.o: In function `cache_as_ram_main': /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/mainboard/asus/f2a85-m/romstage.c:106: undefined reference to `do_smbus_write_byte' collect2: error: ld returned 1 exit status make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1 add `southbridge/amd/agesa/hudson/smbus.c` providing the function `do_smbus_write_byte` to ROM stage in `Makefile.inc`. That can actually be used after the needed header files are included in a previous commit. Change-Id: I89542479c4cf6d412614bcf4586ea98e097328d6 Reported-by: David Hubbard <david.c.hubbard+coreboot@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3200 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-05-10Get rid of a number of __GNUC__ checksStefan Reinauer
In the process of streamlining coreboot code and getting rid of unneeded ifdefs, drop a number of unneeded checks for the GNU C compiler. This also cleans up x86emu/types.h significantly by dropping all the duplicate types in there. Change-Id: I0bf289e149ed02e5170751c101adc335b849a410 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3226 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-10Drop prototype guarding for romccStefan Reinauer
Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1] made romcc not choke on function prototypes anymore. This allows us to get rid of a lot of ifdefs guarding __ROMCC__ . [1] http://review.coreboot.org/2424 Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3216 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-07Intel 82801Gx: LPC: Unify I/O APIC setupPaul Menzel
Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. As commented by Aaron Durbin, a separate `i82801gx_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I104a2d9c2898da14d26f8f2992d5a065ad640356 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3181 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-05-03Intel Lynx Point: Use 2 << 24 to clarify that I/O APIC ID is 2Paul Menzel
Commit »haswell: Add initial support for Haswell platforms« (76c3700f) [1] used `1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which is the same value, makes it clear, that the I/O APIC ID is 2. Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2« (8c937c7e) [2] is used as a template. [1] http://review.coreboot.org/2616 [2] http://review.coreboot.org/3100 Change-Id: I28f9e90856157b4fdd9a1e781472cc4f51d25ece Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3123 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-05-01AMD Hudson A55E: Remove GEC firmware blob kconfig promptBruce Griffith
The "gigabit ethernet controller" (GEC) block was added to AMD Hudson A55E to integrate ethernet capabilities into an AMD southbridge. The GEC is designed to work with B50610 and B50610M gigabit PHY chips from Broadcom. These parts may not be generally available in small quantities for embedded development. The GEC block requires an opaque firmware blob to function. The GEC blob is controlled by AMD and Broadcom and is not available from coreboot.org. This change removes GEC support from AMD Parmer and AMD Thatcher mainboards since these boards do not have the Broadcom PHY. AMD has requested that the GEC be hidden for Hudson FCH since the PHY parts are not generally available. This Kconfig option can make it appear that this is a viable and supported way to add Ethernet to an embedded board. It is possible to use the Hudson GEC block with other PHYs, but this requires development of a custom GEC blob and a custom Ethernet driver. A custom GEC blob has been developed for a Micrel PHY, but there is no accompanying driver. Change-Id: I7a7bf4d41e453390ecf987c9c45ef2434fc1f1a3 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3127 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-26Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2Paul Menzel
Commit »Support for the Intel ICH7 southbridge.« (debb11fc) [1] used `1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which is the same value, makes it clear, that the I/O APIC ID is 2. Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2« (8c937c7e) [2] is used as a template. [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=debb11fc1fe5f5560015ab9905f1ccc2e08c73e0 [2] http://review.coreboot.org/3100 Change-Id: Ib688500944cd78a1cc1c8082bb138fa9468bdbfb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3122 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-18AMD/SB800: Define the GPP PCIe lane distributionDave Frodin
Commit 23023a5 correctly enabled the SB800 GPP PCIe ports but didn't distribute the 4 GPP PCIe lanes amongst the enabled PCIe ports. This fix was verified by openvoid on a AsRock E350M1 motherboard. Change-Id: I0116c5f518e0d000be609013446e53da4112f586 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/3104 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-16Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2Vladimir Serbinenko
Commit »Add support for Intel Panther Point PCH« (8e073829) [1] used `1 << 25` to set the APIC ID of 2. Using `2 << 24`, which is the same value, instead makes it clear, that the APIC ID is 2. [1] http://review.coreboot.org/853 Change-Id: I5044dc470120cde2d2cdfc6e9ead17ddb47b6453 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3100 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-04-15Fam14 DSDT: Also return for unrecognized UUID in _OSCMike Loptien
Fixing warnings introduced by the following patches: http://review.coreboot.org/#/c/2684/ http://review.coreboot.org/#/c/2739/ http://review.coreboot.org/#/c/2714/ These patches were meant to fix the dmesg warning about the OSC method not granting control appropriately. These patches then introduced warnings during the coreboot build process which were missed during the patch submission process. These warnings are below: Intel ACPI Component Architecture ASL Optimizing Compiler version 20100528 [Oct 15 2010] Copyright (c) 2000 - 2010 Intel Corporation Supports ACPI Specification Revision 4.0a dsdt.ramstage.asl 1143: Method(_OSC,4) Warning 1088 - ^ Not all control paths return a value (_OSC) dsdt.ramstage.asl 1143: Method(_OSC,4) Warning 1081 - ^ Reserved method must return a value (Buffer required for _OSC) ASL Input: dsdt.ramstage.asl - 1724 lines, 34917 bytes, 889 keywords AML Output: dsdt.ramstage.aml - 10470 bytes, 409 named objects, 480 executable opcodes Compilation complete. 0 Errors, 2 Warnings, 0 Remarks, 494 Optimizations This patch gives the following compilation status: Intel ACPI Component Architecture ASL Optimizing Compiler version 20100528 [Oct 1 2012] Copyright (c) 2000 - 2010 Intel Corporation Supports ACPI Specification Revision 4.0a ASL Input: dsdt.ramstage.asl - 1732 lines, 33295 bytes, 941 keywords AML Output: dsdt.ramstage.aml - 10152 bytes, 406 named objects, 535 executable opcodes Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 432 Optimizations The fix is simply adding an Else statement to the If which checks for the proper UUID. This way, all outcomes will return a full control package. This patch has no effect on the dmesg output. Change-Id: I8fa246400310b26679ffa3aa278069d2e9507160 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3052 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-11AMD RS780, SR5650: PcieTrainPort: Fix typo *i*gnoring in commentPaul Menzel
Reading the paste of code in a message to the mailing list [1], a typo was spotted and found in one more place. $ git grep egnoring src/southbridge/amd/rs780/cmn.c: * egnoring the reversal case src/southbridge/amd/sr5650/sr5650.c: * egnoring the reversal case These typos are there since when the code was committed and are now corrected. [1] http://www.coreboot.org/pipermail/coreboot/2013-April/075644.html Change-Id: I55c65f71e4834f209b60d678f0d44bc2f4217099 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3062 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-11Persimmon/Fam14/SB800 DSDT: Split into common areasMike Loptien
Split the Persimmon DSDT into common code areas. For example, split the Southbridge specific code into the Southbridge directory and CPU specific code into the CPU directory. Also adding the superio.asl file to the Persimmon DSDT tree. This file is empty for the moment but will be necessary in the future. I have also emptied the thermal.asl file in the mainboard directory because it does not seem to perform as intended (fan control does not change when it is brought back into the code base) and it has been inside a '#if 0' statement for a long time. Removing it until it is decided that it is actually necessary. This change was verified in three different ways: 1. Visual comparison of the compiled DSDT pulled from the Persimmon after booting into Linux using the ACPI tools acpidump, acpixtract, and iasl. The comparison was done between the DSDT before and after doing the split work. This test is somewhat difficult considering the expanse of the changes. Blocks of code have been moved, and others changed. 2. Linux logs were dumped before and after the DSDT split. Logs dumped and compared include dmesg and lspci -tv. Neither log changed significantly between the two compare points. 3. The test suite FWTS was run on the Coreboot build both before and after doing the DSDT split with the command 'sudo fwts -b -P -u'. The flag -b specifies all batch jobs, -P specifies all power tests, and -u specifies utilities. Interactive jobs were not run as most of them consist of laptop checks. Again, there were no significant changes between the two endpoints. These tests lead me to believe that there was no change in the functionality of the ACPI tables apart from what is known and expected. This patch is the first of a series of patches to split the DSDT. The ASRock patch was merged before this one and breaks the ASROCK E350M1 build (patch 8d80a3fb: http://review.coreboot.org/#/c/3050/). Please be aware of this dependency when pulling these patches. Other patches that depend on this patch are 'AMD Fam14: Split out the AMD Fam14 DSDT' (http://review.coreboot.org/#/c/3051/) and 'Fam14 DSDT: Also return for unrecognized UUID in _OSC' (http://review.coreboot.org/#/c/3052/) Change-Id: I53ff59909cceb30a08e8eab3d59b30b97c802726 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3048 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-03lynxpoint: Cosmetic cleanupStefan Reinauer
src/southbridge/intel/lynxpoint/pmutil.c was committed with two things that needed fixing. Change-Id: Ib83343a75840aa29847b607b0275971eb8140f12 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3003 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-04-01lynxpoint: Move ACPI NVS into separate CBMEM tableDuncan Laurie
The ACPI NVS region was setup in place and there was a CBMEM table that pointed to it. In order to be able to use NVS earlier the CBMEM region is allocated for NVS itself during the LPC device init and the ACPI tables point to it in CBMEM. The current cbmem region is renamed to ACPI_GNVS_PTR to indicate that it is really a pointer to the GNVS and does not actually contain the GNVS. Change-Id: I31ace432411c7f825d86ca75c63dd79cd658e891 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2970 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-01lynxpoint: Basic configuration of SerialIO devicesDuncan Laurie
This adds configuration of SerialIO devices in the Lynxpoint-LP chipset. This includes DMA, I2C, SPI, UART, and SDIO controllers. There is assorted magic setup necessary for the devices and while it is similar for each device there are subtle differences in some register settings. These devices must be put into "ACPI Mode" in order to take advantage of S0ix. When in ACPI mode the allocated PCI BARs must be passed to ACPI so it can be relayed to the OS. When the devices are in ACPI mode BAR0+BAR1 is saved into ACPI NVS and then updated and returned when the OS calls _CRS. Note that is is not entirely complete yet. We need to update the IASL compiler in our build environment to support ACPI 5.0 in order to be able to pass the FixedDMA entries to the kernel. There are also no ACPI methods defined yet to do D0->D3->D0 transitions for actually entering/exiting S0ix states. This is hard to test right now because our kernel does not support any of these devices in ACPI mode. I was able to build and test the upstream bleeding-edge branch of the linux-pm git tree. With that tree I was able to enumerate and load the driver for the DesignWare I2C driver and attempt to probe the I2C bus -- although there are no devices attatched. I am also able to see the resources from ACPI in /proc/iomem get reserved properly in the kernel. Change-Id: Ie311addd6a25f3b7edf3388fe68c1cd691a0a500 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2971 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-01lynxpoint: Fix LP clock gating setup for LPCDuncan Laurie
This bit offset is incorrect and should only be set based on another bit in a different register. Change-Id: I6037534236e3a4a5d15e15011ed9b5040b435eaf Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2973 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-01lynxpoint: fix enable_pm1() functionAaron Durbin
The new enable_pm1() function was doing 2 things wrong: 1. It was doing a RMW of the pm1 register. This means we were keeping around the enables from the OS during S3 resume. This is bad in the face of the RTC alarm waking us up because it would cause an infinite stream of SMIs. 2. The register size of PM1_EN is 16-bits. However, the previous implementation was accessing it as a 32-bit register. The PM1 enables should only be set to what we expect to handle in the firmware before the OS changes to ACPI mode. Change-Id: Ib1d3caf6c84a1670d9456ed159420c6cb64f555e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2978 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-01lynxpoint: split clearing and enabling of smmAaron Durbin
Previously southbridge_smm_init() was provided that did both the clearing of the SMM state and enabling SMIs. This is troublesome in how haswell machines bring up the APs. The BSP enters SMM once to determine if parallel SMM relocation is possible. If it is possible the BSP releases the APs to do SMM relocation. Normally, after the APs complete the SMM relocation, the BSP would then re-enter the relocation handler to relocate its own SMM space. However, because SMIs were previously enabled it is possible for an SMI event to occur before the APs are complete or have entered the relocation handler. This is bad because the BSP will turn off parallel SMM save state. Additionally, this is a problem because the relocation handler is not written to handle regular SMIs which can cause an SMI storm which effectively looks like a hung machine. Correct these issues by turning on SMIs after all the SMM relocation has occurred. Change-Id: Id4f07553b110b9664d51d2e670a14e6617591500 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2977 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-01AMD hudson & SB800 - Fix issues with mawkMartin Roth
When calculating the offsets of the various binary blobs within the coreboot.rom file, we noticed that using mawk as the awk tool instead of using gawk led to build issues. This was finally traced to the maximum value of the unsigned long variables within mawk - 0x7fff_ffff. Because we were doing calculations on values up in the 0xffxxxxxx range, these numbers would either be turned into floating point values and printed using scientific notation, or truncated at 0x7fff_ffff. To fix this, we print the values out as floating point, with no decimal digits. This works in gawk, mawk, and original-awk and as the testing below show, seems to be the best way to do this. printf %u 0xFFFFFFFF | awk '{printf("%.0f %u %d", $1 , $1 , $1 )}' mawk: 4294967295 2147483647 2147483647 original-awk: 4294967295 2147483648 4294967295 gawk: 4294967295 4294967295 4294967295 The issue of %d not matching gawk and original-awk has been reported to ubuntu. In the future, I'd recommend that whenever awk is used, a format is specified. It doesn't seem that we can count on the representation being the same between the different versions. Change-Id: I7b6b821c8ab13ad11f72e674ac726a98e8678710 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2628 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01lynxpoint: Rework ACPI NVS to add new SerialIO variablesDuncan Laurie
This reclaims space in ACPI NVS by removing unused fields and adds new fields for SerialIO BARs which will be used to communicate the allocated resources to ACPI. Change-Id: I002bf396cf7b495bc5b7e54b741527e507aff716 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2969 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29AMD CIMx SB800: Update Kconfig help texts to new SATA mode defaultPaul Menzel
In the following commit commit ee5c111755ac4acc6dfb6e10a4e271211e149a39 Author: Paul Menzel <paulepanter@users.sourceforge.net> Date: Tue Mar 12 12:41:40 2013 +0100 AMD CIMx SB800: Enable AHCI mode for SATA controller by default Reviewed-on: http://review.coreboot.org/2661 I forgot to update the help texts to the new SATA mode default. Do so now. Additionally note that help texts for `choice` do not seem to be shown. Change-Id: I17f401633a2136efca2b21a621482e0724ff9f04 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2936 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22Unify setting i82801e LPCKyösti Mälkki
Make it more similar to i82801d LPC init. Change-Id: I7b32747ee8012c220c8628994d749999c144b716 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2545 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-22Fix compilation of Intel LynxPoint based boardsStefan Reinauer
The haswell patches that verified correctly were not yet submitted, but verified correctly. However they still used romcc_io.h which was dropped in another patch earlier today. With a lot of development happening in parallel, this is unfortunately nothing that the gerrit 2.6 Rebase If Necessary submit type could have fixed. Change-Id: Ifef9ae05b22c408e78d6cff37defd68e4ed91ed9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2876 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-22romstage: add support for vboot firmware selectionAaron Durbin
This patch implements support for vboot firmware selection. The vboot support is comprised of the following pieces: 1. vboot_loader.c - this file contains the entry point, vboot_verify_firmware(), for romstage to call in order to perform vboot selection. The loader sets up all the data for the wrapper to use. 2. vboot_wrapper.c - this file contains the implementation calling the vboot API. It calls VbInit() and VbSelectFirmware() with the data supplied by the loader. The vboot wrapper is compiled and linked as an rmodule and placed in cbfs as 'fallback/vboot'. It's loaded into memory and relocated just like the way ramstage would be. After being loaded the loader calls into wrapper. When the wrapper sees that a given piece of firmware has been selected it parses firmware component information for a predetermined number of components. Vboot result information is passed to downstream users by way of the vboot_handoff structure. This structure lives in cbmem and contains the shared data, selected firmware, VbInitParams, and parsed firwmare components. During ramstage there are only 2 changes: 1. Copy the shared vboot data from vboot_handoff to the chromeos acpi table. 2. If a firmware selection was made in romstage the boot loader component is used for the payload. Noteable Information: - no vboot path for S3. - assumes that all RW firmware contains a book keeping header for the components that comprise the signed firmware area. - As sanity check there is a limit to the number of firmware components contained in a signed firmware area. That's so that an errant value doesn't cause the size calculation to erroneously read memory it shouldn't. - RO normal path isn't supported. It's assumed that firmware will always load the verified RW on all boots but recovery. - If vboot requests memory to be cleared it is assumed that the boot loader will take care of that by looking at the out flags in VbInitParams. Built and booted. Noted firmware select worked on an image with RW firmware support. Also checked that recovery mode worked as well by choosing the RO path. Change-Id: I45de725c44ee5b766f866692a20881c42ee11fa8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2854 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Fix up handling for LynxPoint-LP chipsetsDuncan Laurie
This configures power management registers according to the 1.2.0 reference code drop. There are many inconsistencies with the documentation and I tried to note those with ?. This does not do the same for LynxPoint-H yet. Change-Id: I9b8f5c24a8b0931075a44398571c9b0d54cce6a6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2819 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Change sata.c to get rid of #ifDuncan Laurie
This uses the new helper function added earlier. Change-Id: Icdb5d5c51f70eeb7e39e11062276ceb3eb3d9473 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2818 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Fix ELOG logging of power management eventsDuncan Laurie
This is updated to handle LynxPoint-H and LynxPoint-LP and a new wake event is added for the power button. Boot, suspend/resume, reboot, etc on WTM2 and then check the event log to see if expected events have been added. Change-Id: I15cbc3901d81f4fd77cc04de37ff5fa048f9d3e8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2817 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21haswell/lynxpoint: Use new PCH/PM helper functionsDuncan Laurie
This makes use of the new functions from pmutil.c that take care of the differences between -H and -LP chipsets. It also adds support for the LynxPoint-LP GPE0 register block and the SMI/SCI routing differences. The FADT is updated to report the new 256 byte GPE0 block on wtm2/wtm2 boards which is too big for the 64bit X_GPE0 address block so that part is zeroed to prevent IASL and the kernel from complaining about a mismatch. This was tested on WTM2. Unfortunately I am still unable to get an SCI delivered from the EC but I suspect that is due to a magic command needed to put the EC in ACPI mode. Instead I verified that all of the power management and GPIO registers were set to expected values. I also tested transitions into S3 and S5 from both the kernel and by pressing the power button at the developer mode screen and they all function as expected. Change-Id: Ice9e798ea5144db228349ce90540745c0780b20a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2816 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Fix GPIO and PM base reservationsDuncan Laurie
The kernel ACPI was not happy with the Add inside a ResourceTemplate (or perhaps within the IO declaration) Instead make a buffer of IO reservations and turn _CRS into a method that updates the buffer depending on the chipset type. This adds an \ISLP() method that checks the chipset LPC device ID to see if it is -LP or -H. It also increases the PM base reservation to 256 bytes and moves both GPIO and PM base to above 0x1000 on -LP chipsets. Change-Id: I747b658588a4d8ed15a0134009a7c0d74b3916ba Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2815 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: remove DEBUG_PERIODIC_SMISDuncan Laurie
This was put in for debugging and experimentation on i945 and has been copied around since. Drop it from lynxpoint. Change-Id: I0b53f4e1362cd3ce703625ef2b4988139c48b989 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2814 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Add power management helper functionsDuncan Laurie
There are subtle yet significant differences in some of the registers in the power management region between LynxPoint-H and LynxPoint-LP. In order to reduce code that is accessing these registers and would need special cases this adds a number of helper functions that can be used in both ramstage and SMM. This commit just adds the new functions, subsequent commits will start to use them. Change-Id: I411da75da519f5b3198a408078cbf3114e426992 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2813 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Add helper functions for reading PM and GPIO baseDuncan Laurie
These base addresses are used in several places and it is helpful to have one location that is reading it. Change-Id: Ibf589247f37771f06c18e3e58f92aaf3f0d11271 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2812 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Add function for checking for LP chipsetDuncan Laurie
Add a helper function pch_is_lp() that will return 1 if the current chipset is of the new "low power" variant used with Haswell ULT. Additionally these functions are added to SMM so it can be used there. Change-Id: I9acdea2c56076cd8d9627aba66cf0844c56a38fb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2811 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Enable EC IO ports 0x62/0x66Duncan Laurie
In order to be able to talk to an EC via standard path. Change-Id: I3fe76882dec9a0596cbc1c844afa2ddb03ed771c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2810 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: update MBP give up routineAaron Durbin
I'm not sure if I screwed this up originally or the Intel docs changed (I didn't bother to go back and check). According to ME BWG 1.1.0 the give up bit is in the host general status #2 register. Change-Id: Ieaaf524b93e9eb9806173121dda63d0133278c2d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2808 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21LynxPoint: Move RCBA helper function to its own fileDuncan Laurie
So it can get used in both romstage and ramstage. Change-Id: Ief9eaafdd91df2a7b668de1a9b83aea3af3ff894 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2802 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-19lynxpoint: Add cbfs_load_payload() implementationAaron Durbin
SPI accesses can be slow depending on the setup and the access pattern. The current SPI hardware setup to cache and prefetch. The alternative cbfs_load_payload() function takes advantage of the caching in the CPU because the ROM is cached as write protected as well as the SPI's hardware's caching/prefetching implementation. The CPU will fetch consecutive aligned cachelines which will hit the ROM as cacheline-aligned addresses. Once the payload is mirrored into RAM the segment loading can take place by reading RAM instead of ROM. With the alternative cbfs_load_payload() the boot time on a baskingridge board saves ~100ms. This savings is observed using cbmem.py after performing warm reboots and looking at TS_SELFBOOT_JUMP (99) entries. This is booting with a depthcharge payload whose payload file fits within the SMM_DEFAULT_SIZE (0x10000 bytes). Datapoints with TS_LOAD_PAYLOAD (90) & TS_SELFBOOT_JUMP (99) cbmem entries: Baseline Alt -------- -------- 90:3,859,310 (473) 90:3,863,647 (454) 99:3,989,578 (130,268) 99:3,888,709 (25,062) 90:3,899,450 (477) 90:3,860,926 (463) 99:4,029,459 (130,008) 99:3,890,583 (29,657) 90:3,834,600 (466) 90:3,890,564 (465) 99:3,964,535 (129,934) 99:3,920,213 (29,649) Booted baskingridge many times and observed 100ms reduction in TS_SELFBOOT_JUMP times (time to load payload). Change-Id: I27b2dec59ecd469a4906b4179b39928e9201db81 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2783 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-19bd82x6x: Fix compiling with USB debug port supportRonald G. Minnich
At some point, compiles with USB Debug port stopped working. This change makes a trivial reordering in the code and adds two makefile entries to make it build without errors. It also works on stout. Build and boot as normal. Works. Enable CONFIG_USB, connect USB debug hardware to the correct port (on stout, that's the one on the left nearest the back) and watch for output. Change-Id: I7fbb7983a19b0872e2d9e4248db8949e72beaaa0 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: http://review.coreboot.org/2784 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-18lynxpoint: Move a bit of generic RCBA into early_pchDuncan Laurie
Rather than have to repeat this bit in every mainboard. Also, remove the reset of the RTC power status from here. We had done this in TOT for current platforms but did not carry it back to emeraldlake2 where this branched from. If we clear the status here then we don't get an event logged later which can be important for the devices that do not have a CMOS battery. Change-Id: Ia7131e9d9e7cf86228a285df652a96bcabf05260 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2683 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18haswell: Use SMM ModulesAaron Durbin
This commit adds support for using the SMM modules for haswell-based boards. The SMI handling was also refactored to put the relocation handler and permanent SMM handler loading in the cpu directory. All tseg adjustment support is dropped by relying on the SMM module support to perform the necessary relocations. Change-Id: I8dd23610772fc4408567d9f4adf339596eac7b1f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2728 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-17Intel HD Audio: clean up initialization codeStefan Reinauer
- Some initialization steps were done twice - One step was missing for Panther Point HDA - Added a 1ms delay after reset - Increased timeout to 1ms for all codec operations Change-Id: Ib751f1a16ccd88ea2fbbb2a10737f76277574026 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2518 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-17haswell platforms: restructure romstage mainAaron Durbin
There was a mix of setup code sprinkled across the various components: southbridge code in the northbridge, etc. This commit reorganizes the code so that northbridge code doesn't initialize southbridge components. Additionally, the calling dram initialization no longer calls out to ME code. The main() function in the mainboard calls the necessary ME functions before and after dram initialization. The biggest change is the addition of an early_pch_init() function which initializes the BARs, GPIOs, and RCBA configuration. It is also responsible for reporting back to the caller if the board is being woken up from S3. The one sequence difference is that the RCBA config is performed before claling the reference code. Lastly the rcba configuration was changed to be table driven so that different board/configurations can use the same code. It should be possible to have board/configuration specific gpio and rcba configuration while reusing the romstage code. Change-Id: I830e41b426261dd686a2701ce054fc39f296dffa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2681 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-17bd82x6x: Add config option to force SATA link to different speeds.Shawn Nematbakhsh
Certain SATA devices claim to support SATA 6 Gbps, but in fact have bugs. For these devices, add a config option to force the SATA link speed to something other than default. Change-Id: I2dc1793cd58771298a392345162d39d20eb0afbb Signed-off-by: Shawn Nematbakhsh <shawnn@google.com> Reviewed-on: http://review.coreboot.org/2765 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-17Pantherpoint: Add XHCI device initDuncan Laurie
This enables power management and clock gating on XHCI. Change-Id: I124ea6c5aca034b7ec4b5286d971c2adfce25c88 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2761 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-17bd82x6x: don't use absolute symbolsAaron Durbin
objcopy -B provides symbols of the form _binary_<name>_(start|end|size). However, the _size variant is an absoult symbol. If one wants to relocate the smi loading the _size symbol will be relocated which is wrong since it is suppose to be a fixed size. There is no way to distinguish symbols that shouldn't be relocated vs ones that can. Instead use the _start and _end variants to determine the size. Change-Id: I55192992cf36f62a9d8dd896e5fb3043a3eacbd3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2760 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-17Add bd82x6x XHCI(USB3) S3/S4 workaroundMarc Jones
The bd82x6x requires some additional setting on S3/S4 entry. Change-Id: I24489ab94dd7cd5a4a64044f25153f5b01a45b77 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/2759 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-17Add bd82x6x PCH functions to SMMMarc Jones
Add the PCH function to SMM for follow-on SMM patches that require these functions. Change-Id: I7f3a512c5e98446e835b59934d63a99e8af15280 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/2758 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-17lynxpoint: Add support for disabling ULT devicesDuncan Laurie
These enables are hidden behind IOBP for some reason. Boot to linux with SDIO disabled and see that the SDIO driver does not load and crash the system. Change-Id: Icfbfa117e9e57a51d32db7f6366a9d0d790adcf0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2695 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14lynxpoint: lpc resource reservationsAaron Durbin
This commit updates the Lynx Point resource reservations before the coreboot allocator assigns resources. There is no need to mark anything as subtractive decode because there are no devices/buses linked to the LPC device. The I/O range reservations consists of claiming the first 4KiB of I/O space. The PMBASE, GPIOBASE, and LPC generic I/O decode ranges are checked against the default claimed range. If those ranges overlap or fall outside of the default range then those resources are added. The MMIO range reservations consist of claiming everything from the I/O APIC to 4GiB. The RCBA and the LPC Generic Memory range register are then conditionally added if they fall outside of the default MMIO range. Change-Id: I0f560a03814a2b15961fdbe61e4164cd54cff7a5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2682 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14haswell: more ULT/LP support and minor tweaksDuncan Laurie
- Add ME device ID for Lynxpoint LP - Add GPU device IDs for ULT - SATA init tweaks from checking against DXE reference code - Remove the ICH7 from the SPI driver so it works on all lynxpoint without having to add more LPC device ID checks - Add function disable for audio dsp and xhci, remove PCI bridge - Add interrupt route registers for new devices (needs romstage setup) Change-Id: Idb48f50d0bacb6bf90531c3834542b9abb54fb8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2680 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14lynxpoint: Update device IDs and clock gating setupDuncan Laurie
- Add device IDs for lynxpoint mobile and LP variants. - Update the clock gating setup based on BWG - Update the SATA programming based on BWG - Add a DEVSLP0 mux config register Change-Id: Icf4d7bab7f3df7adef5eb7c5e310a6995227a0e5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2649 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-14lynxpoint: Add new GPIO interface for Lynxpoint-LPDuncan Laurie
The low power variant of the chipset introduces a completely new interface to the GPIOs. This is a 1KB region and so needs to be moved as well so it does not conflict with other IO regions. Also expose the gpio_get functions to ramstage and move the prototypes to pch.h so they can be used for both GPIO interfaces. Change-Id: I20bc18669525af16de8cdf99f0ccfa9612be63ad Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2648 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-14lynxpoint: Add Kconfig entry for Low Power chipsetDuncan Laurie
There are enough subtle differences that it is useful to have a Kconfig entry to differentiate the ULT/LP chipet from the desktop/mobile versions. Change-Id: I04ca1bc6f90bcf9e6994ea7125c98347e8def898 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2645 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-14lynxpoint: ME to BIOS Payload UpdatesAaron Durbin
This commit contains a bevy of updates: - PCI device id is updated to match Lynx Point EDS in the ME driver. - Allocate the memory to store the consumption of the MBP. - me_bios_payload structure is now a structure of pointers that point into the allocated memory. - The ICC profile structure was updated to correctly reflect the documentation. Verfied that output of MBP reading can handle unknown items. Change-Id: I43cc45e6b797444c105e7c842eb5684e9c104687 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2641 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14lynx point: add new ME status informationAaron Durbin
According to the 0.8.0 ME BWG this is a new state. It's not very clear what exactly it entails, but the Basking Ridge CRB was tripping it when MRC_DEBUG was enabled (presumably because of a DID timeout). Instead of 0x17 one can now see the proper message for this state. Change-Id: I5bda1de7d3d957d38a4760a02dcd170ec48782e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2640 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14haswell: remove GPIO60 memory reset gate on S3 transitionDuncan Laurie
This is no longer tied to a GPIO but has a proper chipset pin. Change-Id: Iba70338e8c67e3c3c1cb32e69bfea1282fda8cb5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2643 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14haswell: remove explicit pcie config accessesAaron Durbin
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: I8406cec16c1ee1bc205b657a0c90beb2252df061 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2618 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14lynxpoint: PMIR register renameAaron Durbin
The register that controls global reset is named the Power Mangement Initialization Regiser (PMIR). Update the defines to reflect the documentation. Additionally, there is no core well reset control according to the EDS. There is, however, a CF9 lock field to lock this register down. Change-Id: I773c33bec63a06cdb869eb9f94553d476e492798 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2619 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14lynxpoint: Management Engine UpdatesAaron Durbin
The ME9 requirements have added some registers and changed some of the MBP state machine. Implement the changes found so far in the ME9 BWG. There were a couple of reigster renames, but the majority of th churn in the me.h header file is just introducing the data structures in the same order as the ME9 BWG. Change-Id: I51b0bb6620eff4979674ea99992ddab65a8abc18 Signed-Off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2620 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14haswell: add PCI id supportAaron Durbin
In order for coreboot to assign resources properly the pci drivers need to have th proper device ids. Add the host controller and the LPC device ids for Lynx Point. Resource assignment works correctly now w/o odd behavior because of conflicts. Change-Id: Id33b3676616fb0c428d84e5fe5c6b8a7cc5fbb62 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2638 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-14lynxpoint: Update IOBP programming methodDuncan Laurie
This follows the new method outlined in the LPT BWG. It is also very pedantic about its operation so it is easier to read and compare against the docs and the reference code implementation. Change-Id: I235d634cded0c75ec0e9f53488f5b366107a18fa Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2694 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14haswell: Add initial support for Haswell platformsAaron Durbin
The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore, the southbridge support is included as well. The basis for this code is the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires more attention, but this is a good starting point. This code partially gets up through the romstage just before training memory on a Haswell reference board. Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2616 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-12AMD CIMx SB800: Enable AHCI mode for SATA controller by defaultPaul Menzel
The current default is IDE mode which is slower compared to AHCI mode. Therefore use AHCI mode by default. A similar change was made for AMD Persimmon in commit »Enable SATA AHCI for faster boot with SeaBIOS.« (96be74c7) [1] but was indirectly reverted by »sb800: Add sata ahci/raid mode kconfig option« (d4a0e7d0) [2]. [1] http://review.coreboot.org/220 [2] http://review.coreboot.org/225 Change-Id: I4fa31b0a3280891e7a3f37675ae8415205818947 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2661 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-09Add Intel Panther Point USB3 initializationMarc Jones
Add PEI updates and ACPI updates for supporting EHCI to XHCI USB port support. Change-Id: I9ace68a1b3950771aefb96c1319b8899291edd9a Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/2519 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-06AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperioJens Rottmann
The power up default for the 14M_25M_48M_OSC switchable clock output ball of the SB800 chipset is 14 MHz. sb800/bootblock.c changes this to 48 MHz, which is the correct value for almost all SIOs. However, not for 'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz and is not configurable for other clock speeds. A wrong SIO clock supply results in funny RS232 output (wrong bit speed) and non-working PS/2. We could switch back to 14 MHz in the mainboard's romstage.c, but then the clock frequency would change twice. The resulting short 48 MHz burst causes a handful of rubbish characters on RS232 on every boot until the SIO clock has stabilized again. This patch skips the SB800 clock switch if the SIO Kconfig requests 14 MHz. This does not affect any boards currently in the repository (yet). Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2454 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-28Use defines for some i82801ex/gx registersKyösti Mälkki
Change-Id: I0069ec26278b82d61ce5bcfb94d77647dfd3254b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2530 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-27smm: Update rev 0x30101 SMM revision save stateAaron Durbin
According to both Haswell and the SandyBridge/Ivybridge BWGs the save state area actually starts at 0x7c00 offset from 0x8000. Update the em64t101_smm_state_save_area_t structure and introduce a define for the offset. Note: I have no idea what eptp is. It's just listed in the haswell BWG. The offsets should not be changed. Change-Id: I38d1d1469e30628a83f10b188ab2fe53d5a50e5a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2515 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-26Unify setting 82801a/b/c/d IOAPIC IDKyösti Mälkki
Remove obscure local copy of writing the ioapic registers. Change-Id: I133e710639ff57c6a0ac925e30efce2ebc43b856 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2532 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25AMD Southbridge: Add RTC init to lpc_initMike Loptien
Adding RTC init code to the Southbridge initialization code in 'lpc_init'. This initializes the RTC so that the Date Alarm register is set to a valid value (0x00) at startup. By setting the Date Alarm register to 0x00, it does not get evaluated along with the seconds, minutes, and hours when running 'fwts s3'. Information about fwts (Firmware Test Suite) can be found here: https://wiki.ubuntu.com/Kernel/Reference/fwts This is the same edit made to the CIMX SB800 titled 'AMD/Persimmon: Add RTC init to CIMX SB800' with commit ID: c4d3d which can be viewed here: http://review.coreboot.org/#/c/2488/ Change-Id: Iddb7a3cbabe736b511cde03d7dc0a4a0b1c7fd90 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2510 Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-23AMD/Persimmon: Add RTC init to CIMX SB800Mike Loptien
Adding RTC init code to the Southbridge initialization code in 'late.c'. This initializes the RTC so that the Date Alarm register is set to a valid value (0x00) at startup. By setting the Date Alarm register to 0x00, it does not get evaluated along with the seconds, minutes, and hours when running 'fwts s3'. Information about fwts (Firmware Test Suite) can be found here: https://wiki.ubuntu.com/Kernel/Reference/fwts This was tested on a Persimmon but will apply to other mainboards as well. Change-Id: I9a11bc3f9e3f53c46e7a4d72e62ebb0a4ba1bfe4 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2488 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-21AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE'Zheng Bao
Currently the size of the volatile storage for S3 reserved in the image is hardcoded to 32768 bytes. Make that configurable by introducing the Kconfig 'S3_DATA_SIZE'. As the storage space is needed for storing non-volatile, volatile and MTRR data, add a check if the size is big enough. Change-Id: I9152797cf0045c8da48109a9d760e417717686db Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2383 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-20Whitespace: Replace tab character in license text with two spacesPaul Menzel
For whatever reason tabs got inserted in the license header text. Remove one occurrence of that with the following command [1]. $ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[ ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,' [1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2460 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2013-02-19build system: Retire REQUIRES_BLOBPatrick Georgi
REQUIRES_BLOB assumes that all blob files come from the 3rdparty directory, builds failed when all files were configured to point to other sources. This change modifies the blob mechanism so that cbfs-files can be tagged as "required" with some specification what is missing. If the configured files can't be found (wrong path, missing file), the build system returns a list of descriptions, then aborts. Change-Id: Icc128e3afcee8acf49bff9409b93af7769db3517 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2418 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-19AMD S3: Change S3_VOLATILE_POS to S3_DATA_POSZheng Bao
S3_DATA_POS defines address where the whole S3 data is stored. Change-Id: I4155a0821e74a3653caaead890e5fec5677637aa Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2438 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-18AMD S3: Fix typo vol*a*tile in southbridge KconfigZheng Bao
Change non-volitile to non-volatile. Change-Id: Idfc7db3b3dcf078f0f3134fc62679bed439a4fd2 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2437 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-11spi.h: Rename the spi.h to spi-generic.hZheng Bao
Since there are and will be other files in nb/sb folders, we change the general spi.h to a file name which is not easy to be duplicated. Change-Id: I6548a81206caa608369be044747bde31e2b08d1a Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2309 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-22Hudson: Legacy free question is hudson onlyMartin Roth
The "system is legacy free" question accidentally escaped from the hudson Kconfig where it was intended to stay and went coreboot-wide. This puts it back inside the boundries of the hudson southbridge where it belongs. I also commented the endif statements to make it easier to tell where things belong. Change-Id: I49f7a5eadb96d40c6101a93bc390e644617a5654 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2179 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-21Hudson: Cleanup - change SB800 references to hudsonMartin Roth
Go through southbridge/amd/agesa/hudson, thatcher and parmer mainboard directories and change all references to sb800 to reference hudson instead. This is just cleanup and should make no functional difference. Change-Id: Icd6a9a08c4bbf5e1aed394362d24c05811ed1fba Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2177 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-01-21Hudson: Changes to support agesa/hudson for legacy freeMartin Roth
Add Kconfig option for Legacy free and hook it into the parmer AGESA initialization as well as the FADT code. This should really be done inside the southbridge wrapper and not in the mainboard, but for now the code to attach it to is inside the mainboard. Update Kconfig for parmer and thatcher to default to legacy free. Change-Id: Ib899bd02ddc5506caae4aca2c589cc2526638cb8 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2157 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-21Hudson: Changes to agesa/hudson FADT for ACPI 3.0Martin Roth
Update the southbridge/amd/agesa/hudson FADT generation for ACPI 3.0 compliance similar to what was done for cimx/SB800/fadt.c in commit 9aa4389. commit 9aa43892e6899b719fe7f4754901a0eae379a934 Author: Martin Roth <martin@se-eng.com> Date: Fri May 25 12:23:32 2012 -0600 Update SB800 CIMX FADT According to the datasheet, PMA_CNT_BLK is no longer available and PM2_CNT_BLK should not be used. Setup for these has been removed from the table and .h file. Change-Id: Ied8eb1f26b4aa364d051ec5f7ed6f482bb440957 Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/2140 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-09Fix typo in SB800 Kconfig for IMC positionMartin Roth
The cimx/sb800 IMC Firmware location Kconfig option has a typo which would could set it to the wrong location. Change-Id: I38016bebd1bfe6ad6d3f1c02cb1960712fbf4ab2 Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/2120 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-30rs780: Implement `rs780_internal_gfx_disable` and add .disable pcie_opsDenis 'GNUtoo' Carikli
That code will be used to disable the internal GFX card and enable the external PCIe card. The following lines from function `rs780_internal_gfx_enable()` are taken and reversed. /* Disable external GFX and enable internal GFX. */ l_dword = pci_read_config32(nb_dev, 0x8c); l_dword &= ~(1<<0); l_dword |= 1<<1; pci_write_config32(nb_dev, 0x8c, l_dword); It has been tested on the M4A785T-M with the following card inside the PCIe 16x slot: 02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2) Change-Id: I7bd412b987fde98c97464175e2c7a384a8f0fb84 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2065 Tested-by: build bot (Jenkins)
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