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We are seeing ME disabled and ME error events on some devices
and this extended info can help with debug.
Also fix a potential issue where if the log does manage to get
completely full it will never try to shrink it because the only
call to shrink the log happens after a successful event write.
Add a check at elog init time to shrink the log size.
Change-Id: Ib81dc231f6a004b341900374e6c07962cc292031
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1739
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The handling of write enable was not entirely correct,
the opcode needs to be skipped when the controller is
locked down.
Addresses were not getting set properly for erase commands
which seemed to mostly work when the previous command had
set an address.
Tested by adding events to the event log at runtime on a
freslhy flashed device (with locked down SPI controller)
until the log log shrink happens to ensure it does not hang:
hexdump -C elog.event.kernel_clean
00000000 01 00 00 00 ad de 00 00 00 00
for x in $(seq 1 232); do
cat elog.event.kernel_clean > /sys/firmware/gsmi/append_to_eventlog
done
mosys eventlog list | tail -6
154 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
155 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
156 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
157 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
158 | 2012-09-01 13:54:43 | Log area cleared | 1030
159 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
Change-Id: I3a50dae54422a9ff37daefce3632f8bcbe4eb89f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1717
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Now that WREN prefix is handled properly ELOG is able to write
when the SPI controller is locked down.
To test, ensure that runtime SPI write via ELOG is successful by
checking the event log for a kernel shutdown reason code:
5 | 2012-08-27 11:09:48 | Kernel Event | Clean Shutdown
6 | 2012-08-27 11:09:50 | System boot | 26
7 | 2012-08-27 11:09:50 | System Reset
Change-Id: If6d0dced7cb0f5ca7038b3d758f31b856826d30b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1712
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
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The code that attempts to use the opmenu needs to have a special
case for write enable now that it is handled as an atomic prefix
and not as a standalone opcode.
To test, ensure that runtime SPI write via ELOG is successful by
checking the event log for a kernel shutdown reason code:
5 | 2012-08-27 11:09:48 | Kernel Event | Clean Shutdown
6 | 2012-08-27 11:09:50 | System boot | 26
7 | 2012-08-27 11:09:50 | System Reset
Change-Id: I527638ef3e2a5ab100192c5be6e6b3b40916295a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1710
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
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This appears to fix an infrequent resume hang on Ivybridge.
Tested on 2 devices with 15k suspend/resume cycles each
Change-Id: I53618bc7966824413f1720a2be3cbd2550e29473
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1704
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
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HPET's min ticks (minimum time between events to avoid
losing interrupts) is chipset specific, so move it to
Kconfig.
Via also has a special base address, so move it as well.
Apart from these (and the base address was already #defined),
the table is very uniform.
Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1562
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
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Also deletes files not included in build:
src/southbridge/amd/cimx/sb700/chip_name.c
src/southbridge/amd/cimx/sb800/chip_name.c
src/southbridge/amd/cimx/sb900/chip_name.c
Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1473
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
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The name is derived directly from the device path.
Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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The names were set at various times during development, but
the way the code works, you might end up with the wrong name
being displayed in the logs. Instead of doing magic, just
display both names for each component
Change-Id: I1f8ce44d156442f5f7d717e1a2b47ed1218d4527
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1413
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Move beep commands to board-specific area as they need to be different for
different codecs.
Change-Id: I2a1ac938c49827cc816a95df10793a7e234942bf
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Reviewed-on: http://review.coreboot.org/1410
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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In accordance to PCH EDS 14.1.35.1
Change-Id: I2e6cec6d4f49f404e33a171a8fbd6e4880327896
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1411
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Compilation fails with set_debug_port undeclared in ramstage and
smm code. Fix that by adding usb_debug.c to the appropriate stages.
Change-Id: I2a037d3c5fab76ae6ea65c3a7f4d4e7561bb6d34
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1376
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Our driver infrastructure became more flexible recently.
Make use of it.
These are the low hanging fruits (files with 5 device
variants or more), but there are still lots of files
with less potential for deduplication.
Change-Id: If6b7be5046581f81485a511b150f99b029b95c3b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1358
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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We used a hard coded value for some reason. Don't do that, but use CMOS
instead.
Modelled after http://review.coreboot.org/#/c/443 to get bd82x6x in
sync.
Change-Id: I36d715310157b9f9074f2a1c80710f85833020b4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1324
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This will log if the ME is disabled or has an error.
1) disable ME via EC console: gpioset PCH_HDA_SDO 1
2) boot the device
3) read eventlog with "mosys eventlog list"
71 | 2012-07-13 10:10:55 | Management Engine | Disabled
Change-Id: I9f6ee452d2aea76e6a5ea2cd50a50ff36245692a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1345
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This will allow various teams to select which thermal sensor
will control the thermal zones.
Also add a method to notify the thermalzones of a change
so these threshold/sensor methods take effect.
Needs a modified BIOS that uses the NVS TMPS value in
the thermalzone to read a different sensor.
Then, use a kernel driver that contains the following:
/* Adjust temperature sensor id to 2 */
union acpi_object param;
struct acpi_object_list input;
param.type = ACPI_TYPE_INTEGER
param.integer.value = 2
input.count = 1;
input.pointer = ¶m;
acpi_evaluate_object(NULL, "\\TMPU", &input, NULL);
And ensure that the temperature sensor that is being
monitored switches to ID 2.
Change-Id: I6319741358ba31eb8a3dc635d64f3f0acf683386
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1340
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The ME device was being sent EOP and the PCI device hidden during
coreboot so it was not available in the SMI finalize step.
This also flips the PCI vendor/device dword around for the match.
Boot on Panther Point with serial and SMI debugging enabled and see
that ME EOP message is sent and the device is hidden at end of
U-boot and before the kernel loads.
Finalizing Coreboot
SMI# #0
ME: mkhi_end_of_post
ME: END OF POST message successful (0)
PM1_STS: TMROF
PM1_EN: 120
Starting kernel ...
Change-Id: I230038c62c50db2a1c94078c0a2a67bdc232440e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1338
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The LPC bus normally allocates the range for legacy devices,
0-0x1000. Some devices on LPC are above that range and need to
be accounted for. Check the decode range settings for addresses
> 0x1000 and reserve them.
Change-Id: Idba800d7cee3185296f29dd237ba306f3de8de55
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1337
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Events are logged for SMIs that trigger ACPI sleeps state
entry and when the power button press triggers an SMI such
as at the developer/recovery screens.
Generate ACPI sleep state events and power button
events and verify they show up in the log:
153 | 2012-06-23 17:12:59 | ACPI Enter | S5
184 | 2012-06-23 17:15:50 | ACPI Enter | S3
216 | 2012-06-23 17:28:58 | Power Button
Change-Id: Iba134d619780e459bce189d36d57844997ffb009
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1320
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Unfortunately the drive strength values are very much board
specific and different between mobile and desktop so we don't
try to do any fancy detection here but let it be specified
directly in the devicetree.
Change-Id: I66674bff0de04ecd088fb09afad1cf801a374df2
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1347
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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In order to support the GSMI interface the SMI handler needs
to find and use the state save area from the same CPU that
initiated the SMI. In this case it is a synchronous SMI
resulting form an IO write to port 0xB2.
To find the right CPU state save area iterate over the region
until the "IO Misc Info" field reports the expected value and
then proceed to use that state save area.
This is needed because the coreboot SMI handler only executes on
one core, and that core is non-deterministic. It is likely that
the core executing the C SMM handler is not the same one that
actually did the IO write to 0xB2 and generated the SMI.
The GSMI parameter buffer is passed as a pointer to EBX in the
tate save area, and the GSMI command is extracted from EAX before
it is used as the return value.
This interface is tested by enabling CONFIG_GOOGLE_GSMI in the
kernel and generating events and verifying that they end up
in the event log.
159 | 2012-06-23 16:22:45 | Kernl Event | Clean Shutdown
184 | 2012-06-23 17:14:05 | Kernl Event | Oops
185 | 2012-06-23 17:14:05 | Kernl Event | Panic
Change-Id: Ic121ea69e9f50c88467c435e095c3e3629989806
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1317
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This is a temporary workaround so the SPI bus can be accessed
at runtime in SMM code until the SPI opcode menu is used
properly.
Change-Id: I93d188c55b66d8dce49fa91a1de53ee195944b30
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1318
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This is called from the SMI handler install because those
setup functions clear many of these registers.
Ensure that these events show up in the log as appropriate.
Example log output:
159 | 2012-06-23 14:31:54 | SUS Power Fail
160 | 2012-06-23 14:31:54 | System Reset
161 | 2012-06-23 14:31:54 | ACPI Wake | S5
Change-Id: I48c423c10ee7e6c2829bcc95f6cfabb4979c25a9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1319
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This function is exported so it can be used in other
places that need similar relocation due to TSEG.
Change-Id: I68b78ca32d58d1a414965404e38d71977c3da347
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1310
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ic5aada423d8e61abbebfcaaf5cb02ede80dfae02
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/1339
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
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This was introduced when porting the SPI driver over from u-boot but it
is not needed. Hence drop the extra typedef and use device_t instead.
Change-Id: I3ab797a8e482d1c9aa1d004e488e99aeaffcdd8b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1331
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
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CPUs with configurable TDP will run the TSC at the max non-turbo
ratio for the maximum TDP value, which can cause issues if another
TDP is desired. To deal with this we set the flex ratio to the
nominal TDP ratio early in the boot and then configure the Soft
Reset Data registers so the PCH can tell the CPU what frequency
to run at after a reset.
This is done very early in the bootblock because it is necessary
to reset the system after setting a flex ratio.
The end result is that the TSC will now increment at the max
non-turbo frequency for the nominal TDP.
On some system with 1.8GHz CPU ensure that the kernel
detects the CPU speed as ~1800mhz rather than ~2300mhz:
> dmesg | grep "MHz processor"
[ 0.004000] Detected 1795.801 MHz processor.
Change-Id: I8436dced9199003b6423186a2b041e3f7b84ab8c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1329
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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There are enough differences that it is worth defining the
proper map for the sandybridge/ivybridge CPUs. The state
save map was not being addressed properly for TSEG and
needs to use the right offset instead of pointing in ASEG.
To do this properly add a required southbridge export to
return the TSEG base and use that where appropriate.
Change-Id: Idad153ed6c07d2633cb3d53eddd433a3df490834
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1309
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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- add Kconfig option for CONFIG_SPI_FLASH_SMM
- compile subsystem and chip drivers for smm if enabled
- change mdelay(1) to udelay(500) since mdelay is not defined
in SMM and a 1ms delay is worth avoiding
- make flash chip structure non-const so the probe function
pointers can be relocated for use in TSEG
- Make SMM PCI access possible in southbridge SPI code
Change-Id: Icfcbbe8e4e56658769d46af0b5bf6c79a6432641
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1313
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The ME needs to be talked to through the PCIe memory mapped config
space.
Change-Id: Ic2c5a572a126722a08a82d95df13d11507586c6b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1284
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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In the short term there might be devices with Sandy Bridge CPUs
on mainboards with Panther Point PCHes. While this configuration
option is perfectly valid, coreboot currently ties Sandy Bridge to
Cougar Point and Ivy Bridge to Panther Point. One occurence is in
the ME handling code.
To make coreboot most flexible, compile both ME handlers into
coreboot and decide at runtime which one to use.
Change-Id: Icffe2930873f67c99c3f73e37e7a967f4f002b88
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1280
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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- On Cougar Point there may have been stack corruption during the
ME hash verification
- On Panther Point the ME firmware hash was not passed on to the
OS
Change-Id: I73fc10db63ecff939833fb856a6da1e394155043
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1279
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The PCIe device enable function prints when it disables a device.
The PCIe ports(bridges) use a different routine that didn't print
the message. Add it to be consistent and to provide better debug
output.
Change-Id: I8462c48e7f4930db68703f0bfb710c01c9643a98
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1326
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
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Changing CMOS value for power-on-after-power-fail was only honored
after reboot, which is counter intuitive (set from "enable" to
"disable",
power-off, replug device -> device turns on; and similar cases).
Modelled after http://review.coreboot.org/#/c/444
Change-Id: I2b8461dff1ae085c1ea4b4926084268b4da90321
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1323
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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The function was too eager shifting stuff around, this change corrects
the problem.
Change-Id: I4c13dbe86cb627835dae05bb74af9867c28e143d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1291
Tested-by: build bot (Jenkins)
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There are enough subtle differences in the magic values that
it is easier to make a separate function.
This fixes a reset hang with pantherpoint chipset.
Change-Id: I02b03cb37e5fd5ee2fd62067644f0a62dc2cd26a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1322
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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This makes it available early in romstage without having to
worry when the different romstagse enable it.
Check for extended CMOS to be enabled in early romstage.
This is used by a later commit which uses the extended
CMOS region for stoage.
Change-Id: I9e026d48499c63d6503c2b020d4cc3047126fa93
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1306
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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- Convert all PCI ID lists to new scheme
- Unify code (variable names)
- add missing PCI IDs for Panther Point PCIe root ports.
Change-Id: I6357f6ebce7ddffe45a3ec642b0c594147f6134c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1301
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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This lets the SPI driver and the LPC driver know about HM70 and NM70.
Change-Id: Id2f1e0e5586a2f7200b2d24785df3f2be890da98
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1300
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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We don't ever free memory in coreboot, hence drop spi_flash_free() and
spi_free_slave()
Change-Id: I0ca3f78574ceb4516e7d33c06ab1a58abfb3b0ec
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1273
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Required for Supermicro X7DB8, which needs the FBDIMM clock generator
setup during romstage.
Change-Id: I30ca8354087e851487aee0614595782131d4d9bc
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1116
Tested-by: build bot (Jenkins)
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i3100/i5000 have a second IOAPIC which handles IRQs for PCI-X.
Add code to enable it.
Change-Id: Ib447628f501b152c8adc9c7c89bd09b5615b9e5a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1118
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This change adds utility functions which allow to read any GPIO pin,
as well as a vector of GPIO pin values.
As presented, these functions will be available to Sandy Bridge and
Ivy Bridge systems only.
There is no error checking: trying to read GPIO pin number which
exceeds actual number of pins will return zero, trying to read GPIO
which is not actually configured as such will return unpredictable
value.
When reading a GPIO pin vector, the pin numbers are passed in an
array, terminated by -1. For instance, to read GPIO pins 4, 2, 15 as a
three bit number GPIO4 * 4 + GPIO2 * 2 + GPIO15 * 1, one should pass
pointer to array of {4, 2, 15, -1}.
Change-Id: I042c12dbcb3c46d14ed864a48fc37d54355ced7d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1049
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I98b05d9e639eda880b6e8dc6398413d1f4f5e9c3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1048
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Right now coreboot compilation fails when SPI flash debugging is
enabled. Fix it by using the right set of memory functions.
Change-Id: I5e372c4a5df53b4d46aaed9e251e5205ff68cb5b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1044
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Experiments have shown that writing plain value of 6 at byte io
address of 0xcf9 causes the systems to reset and reboot reliably.
Change-Id: Ie900e4b4014cded868647372b027918b7ff72578
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1050
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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This driver is taken from u-boot and adapted to match
coreboot. It still contains some hacks and is ICH specific
at places.
Change-Id: I97dd8096f7db3b62f8f4f4e4d08bdee10d88f689
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/997
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +
Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +
Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +
Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +
(and some manual changes to fix false positives)
Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
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The current early PM setup that attempts to configure dynamic clock
gating relies on PCIe functions to be enabled that may not be.
Instead of reading port 0 or 4 directly to determine the link width
use the register that refelects the soft strapping options as this
will always be available.
Also add a clear register assignment and break for port 0 in the
switch statement instead of falling through to port 4 as that could
end up setting the slot power limit based on port 4 values instead
of based on port 0.
register 0xE1=0x3f and all other root ports should have 0xE1=0x03.
When port 0 and 4 are disabled they will have 0xE1=0x3C before
being disabled by the pch enable handler.
LUMPY default:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
pci_read8 0 0x1c 0 0xe1
0x3f
pci_read8 0 0x1c 3 0xe1
0x03
LUMPY with PCIe port coalesce enabled:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
pci_read8 0 0x1c 0 0xe1
0x3f
pci_read8 0 0x1c 1 0xe1
0x03
Change-Id: I33a37b0ec0c8e570cf5d9dda2c06e0225fee135c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/980
Tested-by: build bot (Jenkins)
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Background: The PCI spec (3.0-3.2.2.3.4) requires that PCI devices
implement function 0. The Linux Kernel therefore will not enumerate
a PCI device if it does not present a valid config space at function 0.
If a board does not have anything connected to root port 0 and it is
desired to disable the unused ports in order to save power then this
will cause the other downstream PCIe devices to go missing as they
will not be enumerated.
Intel chipsets provide a way to map root port numbers to different PCI
function numbers, thereby avoiding this issue and allowing root port 0
to be turned off.
This change adds a new chip config option 'pcie_port_coalesce' that
will collapse the enabled root ports into a linear map starting at
zero. This option defaults to disabled as it can have a confusing
effect on the system as the declared static devicetree may not match
what is seen at runtime. This option is also forced on if the static
devicetree disables port 0.
When each root port is processed in the early enable stage it looks
for a lower numbered root port that has been disabled and then swaps
the two assigned function numbers.
However the mapping register is write-once so it has to keep track of
the proposed mapping changes until all ports have been processed
before writing out the final map value. At this point it also updates
the function numbers in the static device tree so they are consistent
with the new layout.
There are a few other closely related fixes in this change:
1) There is a power savings opportunity if an entire bank of ports
(0-3 or 4-7) are disabled. This was checking the chipset revision to
look for CougarPoint B1+ stepping and that was not passing on
PantherPoint where this should always be applied. To fix this I added
a function to determine the chipset type based on comparing the upper
byte of the device ID.
2) Apply the same chipset type check fix to the IOBP programming.
3) There is another power savings opportunity to enable dynamic clock
gating on shared PCIe resources which only applies to ports 0 and 4.
However if 0 or 4 is disabled then the later check to enable this
would fail as that device is already hidden.
LUMPY current:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
01:00.0 Network controller: Atheros Communications Inc. Device 0030 (rev 01)
02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B
LUMPY with PCIe port coalesce enabled:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
01:00.0 Network controller: Atheros Communications Inc. Device 0030 (rev 01)
02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B
Change-Id: I828aa407fdc9c156c1c42eda8e2d893c0aa66eef
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/979
Tested-by: build bot (Jenkins)
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The chipset enforces static-defined interrupt swizzling on PCIe root
ports so if a port is remapped to a different function it needs to
still report the proper interrupt map to the OS instead of assuming
that function number is equivalent to root port number.
This change also includes an update to the PCH function disable
register which was incorrect for CPT/PPT and would cause unpredictable
behavior if used.
The kernel command line was changed to add 'nomsi' in order to force
PCIe devices to use IO-APIC assigned interrupts and not MSI to ensure
that the mapping is correct.
LUMPY current:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
16: 41518 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k
19: 720 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0
LUMPY with PCIe port coalesce enabled:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
16: 38988 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k
19: 347 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0
Change-Id: Ia5f6bb8888b5c38a5dbc88bb25ecdf1fca41ee3e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/978
Tested-by: build bot (Jenkins)
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The sata controller comes up in legacy/normal mode and
is currently put into AHCI mode in romstage.
If that is removed and the controller is left alone until the
ramstage driver (like we do on Stumpy/Lumpy) then the resource
allocator will have configured the device for IDE mode with an
IO address in BAR5. Then when the ramstage driver puts the
controller into AHCI mode it will not have the correct resources
to do the rest of the AHCI setup.
So the controller mode needs to be changed in the enable stage
rather than in the init phase. This same register contains
the port map and it is a R/WO (write once) field so the configured
port map must be written at the same time. For non-AHCI mode
the devicetree map was ignored before but it is used now.
Since the port map register is now written at enable step it
does not need to be written again during init.
With this change the sata port map can be reduced to just port 0
and then U-boot does not have to probe all available ports.
Change-Id: I977952cd88797ab4cea79202e832ecbb5c37e0bd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/977
Tested-by: build bot (Jenkins)
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The OS does not re-execute the APMC 'enable ACPI' SMI
on resume so this has the potential to leave things
in an unknown state.
Change-Id: Iaf0fcb99f699e9e0ecacaab3f529026782a95151
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/971
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This adds the PCI device id of the LPC controller identifying the
QPRJ/QS stepping of the Panther Point southbridge.
Change-Id: Idcaa7dbd30224e3690ea469c6cb74f75de287631
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/968
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Many PCI devices share the very same driver despite having different
PCI device IDs, which causes a lot of copy and paste of driver
definitions.
This change introduces a way to specify the array of acceptable
device IDs in a single driver entry. As an example the Intel
{Sandy|Ivy} Bridge SATA driver is being modified to use a single
driver structure for all different SATA controller flavors, a few
more Ivy Bridge IDs are being added as well.
BUG=none
TEST=manual
. modified coreboot brought up an Ivy Bridge platform all the
way to Linux login screen.
Change-Id: I761c5611b93ef946053783f7a755e6c456dd6991
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/982
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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post_code() was added in our internal tree by duplicating code. It's not of
much use at this point, since the code is quite well tested, so avoid bloating
the bootblock (since compiled with ROMCC).
Also add some missing include files that didn't seem to be needed with an
older version of coreboot.
Change-Id: Id62b838728a247e8bcadb4f1db17269be0d4f3f4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/936
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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rename from mainboard_apm_cnt to mainboard_smi_apmc to match the function
naming scheme of the other handlers. Add prototype for mainboard_smi_sleep
(mainboard specific S3 sleep handlers in SMM) that is required by Sandybridge.
Change-Id: Ib479397e460e33772d90d9d41dba267e4e7e3008
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/933
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Add early_smbus.c for romstage-y list and remove respective
include on mainboard romstage.c files.
Tested on AOpen board.
Change-Id: I1c7e6cb32e3a9d7cc9b6037dc27e59149d492001
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/909
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Made using coccinelle:
@@
expression E;
@@
-(E + 7) & -8
+ALIGN(E, 8)
@@
expression E;
@@
-(E + 15) & -16
+ALIGN(E, 16)
Change-Id: I071d2c98cd95580d7de21d256c31b6368a3dc70b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/910
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Some places still hardcoded the address instead of using IO_APIC_ADDR.
Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Change-Id: Iac3cd25b36493bb203e849674320e113cc5fce32
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/853
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Changing CMOS value for power-on-after-power-fail was only honored
after reboot, which is counter intuitive (set from "enable" to "disable",
power-off, replug device -> device turns on; and similar cases).
Change-Id: If1d88c1c34c3333b636ed3ec1e1fb9bea394e615
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/444
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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We used a hard coded value for some reason. Don't do that, but use CMOS
instead.
Change-Id: Ib83aa07a3e55bed075150354a060317ebc9d5ba7
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/443
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: Ifba0b65d81af60774f368d151e935ae1cc768336
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/662
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I83105e92d1cc5d2d12aede564a1ab9c5d912ac56
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/664
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
|
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No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I521deecf58e5d5de303f1ef2f5ff7e965294de18
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/665
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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The current directory is always part of the search path of cpp when
using #include "..."
Change-Id: I74fe39e0c79835e4b9a927afcbeab21040d8ae52
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/648
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Fix issues reported by new lint test.
Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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No in-tree 82801dx-using board has it not selected, so move
selection from boards to southbridge.
Change-Id: I69671cb6411a6cd9c791059ae9546dff3aff702c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/655
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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without it, you can't boot from PCI devices like scsi controllers
which require an interrupt set. So preconfigure all pci devices.
Change-Id: I2cd781227701e8363d83bd90e0e36994359fc194
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/603
Tested-by: build bot (Jenkins)
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BIOS needs to set the bit mask which ports are iplemented on the
board. Without setting this option, seabios fails to boot from
SATA.
Change-Id: I21de3fde3a9cff7c590226f70fa549274f36e2a8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/601
Tested-by: build bot (Jenkins)
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i3100 misses the magic SATA init sequence, which makes all
requests fail. Captured from the vendor BIOS, which writes
those bits on all configurations.
Change-Id: I293b7d9cd681181311ecaced6d7df9b2706c711f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/600
Tested-by: build bot (Jenkins)
|
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Change-Id: I6b612dbd3eb6e8cc45f1c7abca85732fb64de98c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/531
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
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and remove it from mainboard/intel/mtarvon, as this function
is implemented in the southbridge code.
Change-Id: Id3669aaf99b96b4a7a965f4957e5de7c365acaa6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/469
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
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- move enable_usbdebug() declaration to usbdebug.h
- reinitialize debug driver in ramstage, as copying the data
structure from romstage doesn't work right now. This way of copying
data from romstage to ramstage is really board/cpu specific, and is
likely to break often. So don't do it.
Change-Id: I394678ded6679c1803e29eb691b926182bdcab68
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/355
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and
all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n.
This might break a couple of boards on runtime, but so far, fixes were
quite simple.
There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be
adapted.
Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/320
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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The code used PCI register 0x92 to enable sata ports,
which is wrong. The ICH7 documentation states:
"This register is only used in systems that do not
support AHCI. In AHCI enabled systems, bits[3:0] must
always be set (ICH7R only) / bits[2,0] must always be set
(Mobile only), and the status of the port is controlled
through AHCI memory space."
Writing 0x0f to ICH7-M doesn't seem to hurt, so lets write
0x0f for both variants. This patch makes sata_ahci work on
my Thinkpad T60 and X60s.
Change-Id: If3b3daec2e5fbaa446de00272ebde01cd8d52475
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/340
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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If this bit is set, ich7 will enter C4 mode if possible instead of
C3. See ich7 specification (LPC controller, Power management control
registers) for more details.
Change-Id: I352cccdbc51ff6269f153a4542c7ee1df0c01d22
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/329
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: Icbfc47a8d7bfe1600e4212b26e99b2a604de9ef7
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/326
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Doing it this way will break all subsequent smbus calls, because
the smbus code still uses res->base, which points to the old base
address. Fix this by allocating a proper resource.
Change-Id: I0f3d8fba5f8e2db7fe4ca991ef2c345aff436ea4
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/325
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)
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This was mentioned several times already, how about we get it in?
It avoids cbfstool to fail because path/to/"file" doesn't work.
Change-Id: Ia01acbd78f81a5db890fd1573a2f3cbe1450562f
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/305
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
|
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Patch is required to compile this with romcc.
Change-Id: I5c4c0f5b32e5edeb8c48d8455b3493ca79f8b452
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/291
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
|
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Change-Id: I2a3aaf10e453fa6cce8a993356f2a0587178209a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/276
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
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Change-Id: I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/262
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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LXBIOS and LXB-DSDT are not used in other parts of the tree.
Make names consistent across the tree.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I91caeac09fd2401a36e53bd061d249b236a48e43
Reviewed-on: http://review.coreboot.org/224
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP
Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2
uses the same acpi wakeup vector as S3.
Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink
the power LED while sleeping.
acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because
it is used in both romstage and ramstage after patch 3/3, whereas
i82371eb_early_pm.c is used only in romstage.
I used the name acpi_get_sleep_type instead of acpi_is_wakeup_early
because I think acpi_is_wakeup_early is a bit misleading as a name since it
doesn't return a boolean value.
Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the
added check for acpi_slp_type == 2 (resume from S2) should not
change behaviour of other boards:
northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type;
northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0;
northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3;
northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0;
southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type;
southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type;
southbridge/via/vt8237r/vt8237r_lpc.c:238: acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
southbridge/via/vt8237r/vt8237r_lpc.c:239: printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
Change-Id: I13feff0b8f49aa988e5467cdbef02981f0a6be8a
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/188
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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My Thinkpad appeared dead. After investigation, it turned out
that the RTC Alarm was triggering an RTC PM1 SMI, but the SMI
handler didn't read the status register, so it was triggered again.
This is a really nasty situation, as it means you have to dissemble
your Notebook just to unplug the RTC battery.
Change-Id: I5ac611e8a72deb5f38c86486dbe0693804935723
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/67
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Overwriting the SMM Area on resume leaves us with
all variables cleared out, i.e., the GNVS pointer
is no longer available, which makes SMIF function
calls impossible.
Change-Id: I08ab4ffd41df0922d63c017822de1f89a3ff254d
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/34
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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We're using '0xcafed00d' all over the code as magic for ACPI S3
resume. Let's add a define for that. Also replace 0xcafebabe by
a define.
Change-Id: I5f5dc09561679d19f98771c4f81830a50202c69f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/33
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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disabling ACPI during S3 wakeup breaks ACPI wakeup, as the
Host OS is assuming that ACPI is enabled.
Change-Id: I8ced72c4b553d41a57f26d64998118e8a77621f8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/7
Tested-by: build bot (Jenkins)
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in the current code, the defines for the APM_CNT (0xb2) register
are duplicated in almost every place where it is used. define those
values in cpu/x86/smm.h, and only include this file.
And while at it, fixup whitespace.
Change-Id: Iae712aff53322acd51e89986c2abf4c794e25484
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/4
Tested-by: build bot (Jenkins)
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motherboards can use this hook to get notified if someone writes
to the APM_CNT port (0xb2). If the hook returns 1, the chipset
specific hook is also skipped.
Change-Id: I05f1a27cebf9d25db8064f2adfd2a0f5759e48b5
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/3
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
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Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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to unify calls to *_enable_usbdebug()
* rename *_enable_usbdebug() to enable_usbdebug()
* move enable_usbdebug() to generic romstage console init code
and drop it from the individual romstage.c files.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html
It's about time we follow this advice.
Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and
drop unused CPP define
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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There's an off-by-one error in the ACPI GP_LVL declaration:
it declares GL00 with a bit count of 6, and continues with GP07
afterwards. This should be GP06, as the first bitfield covers
GP00-GP05.
While at it, change it to GP00-GP05, as right now GL00 isn't used,
and single bitfield are more usable here.
Also adjust the Getac P470, as this is the only user of those defintions
right now.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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all boards to the new config scheme.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This is so that boards can determine them on runtime based on hardware
properties, if so desired.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Joseph Kellermann <Joseph.Kellermann@heitec.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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already used the new order)
This is in reponse to feedback that the original setup was too complicated.
New cbfs-files-y behaviour:
cbfs-files-y contains the names of files as they appear in CBFS. The
arguments describe the on-filesystem name, the type and (optionally) the
position. Example:
cbfs-files-y += foo
foo-file := bar
foo-type := splashscreen
foo-position := 0xffff8000
This configures a CBFS file called "foo" that is marked "splashscreen",
located at 0xffff8000 in flash and contains the data of the file "bar"
in the filesystem (either in the current directory, ie. where the
corresponding Makefile.inc resides, or if that doesn't exist, relative
to the toplevel directory).
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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