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Modify the dependencies for `SOC_INTEL_CSE_RW_UPDATE` and
`ME_REGION_ALLOW_CPU_READ_ACCESS` config options to include
`SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD`.
This allows these features to be enabled even when CSE sync is performed
in the payload, not just within coreboot (when `SOC_INTEL_CSE_LITE_SKU`
config is enabled).
BUG=b:305898363
TEST=Builds and boots successfully:
* google/rex0 with SOC_INTEL_CSE_LITE_SKU
* google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
Change-Id: Id6ec19d74237f278e8383c89923523871b2cc2db
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Allows to use this driver for the SMBus console without sending an index
byte for every sent char (i.e. !CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER).
Tested with WiP VIA CX700-M2 port and FT4222H as receiver.
Change-Id: Ic368ef379039b104064c9a91474b188646388dd2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82763
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit 88decca14f84 ("ACPI: Add helper fill_fadt_extended_pm_io()")
moved the population of the extended FADT to a separate function, but
incorrectly placed that function call before various length fields were
populated, leading to spurious validation errors in the cbmem boot log.
Correct this by moving the call to fill_fadt_extended_pm_io() after
the required fields are populated.
TEST=build/boot google/slippy (wolf), verify no FADT errors in cbmem
console log.
Change-Id: I1f8522e4813e6071692206f2b7ad2a2f5086071e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83035
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Looks like PCIe root port device IDs for 9-series PCH-H are missing from
commit 434d7d45829e (sb/intel/lynxpoint: Add PCI DIDs for 9 series PCHs)
for some reason. Add them, so that coreboot performs PCIe initialisation
for 9-series PCH-H.
Change-Id: I1589418e5e25daabbf09c66c637e9c4f86aa02a6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82947
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove USB configurations and data structures from northbridge
devicetree (SNB+MRC boards) and bootblock/romstage C code
(native-only SNB boards). All USB configurations are drawn from
southbridge devicetree going forward.
Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Transfer all USB responsibilities to southbridge/intel/bd82x6x,
using one set of USB port configuration supplied by mainboards
in the southbridge section of their devicetree.
For MRC raminit, export southbridge_fill_pei_data() as a hook for
southbridge code to implement. With new code via this hook, bd82x6x
fills pei_data based on this one set of USB port config.
For native raminit, early_usb_init() now goes directly to the devicetree
and no longer get passed an address to it.
TEST=abuild passes for all affected boards. All USB ports still work
on asus/p8x7x-series/v/p8z77-m.
Change-Id: I38378c7ee0701abc434b030dd97873f2af63e6b0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81881
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace 3 unused values in the map with those found during a Ghidra
examination of MRC binary, and on hardwares running vendor firmware
(asus/p8z77-m and HP Z210 CMT Workstation).
The outgoing values were introduced in commit 216ad2170ca8
("sb/intel/bd82x6x: Add new USB currents") in anticipation for
Gigabyte GA-Z77-DS3H mainboard, but effort to land it was eventually
abandoned. Since commit xxxxxxxxxxxx, such values can be placed
directly in the port config, so there should be no hurdle should that
effort be resurrected.
Add a few #defines in pch.h to place some inline documentation
on MRC values, but more will be documented in the future when this
mapping is introduced MRC-side.
Finally, update autoport to match.
Change-Id: I195c7f627994e48f7a6e6698589504dc96248cff
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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This is the first step to:
- Move USB port configs, which are static, from C code to devicetree;
- Unify USB port configs between MRC and native code path.
Change-Id: I59af466d41790e2163342cac8676457ac19371ea
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81878
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For USB to work under native code path, the USB port config needs to
include a current setting for each port, which gets mapped to an
initialization value that gets programmed into the USBIRx register
for the respective port. This map resides in early_usb.c.
The need to update it, whenever we see a previously unaccounted for
initialization value, is getting out of hand.
Instead this patch will allow specifying those values, presumably
taken from an inteltool dump while running vendor firmware,
directly in the USB port map.
Because all USBIRx values are always in the 0x20000yyy form, we only
need the lowest 12 bits. We have more than enough space in the USB
port config structure for this.
As the lowest yyy value we saw so far is 0x53, a note is included to
limit the map to not more than 80 entries. Any value that is too big
to be an index into the map is programmed directly, + 0x20000000, into
the registers.
This opens the future possibility to use the map for a simpler
mapping for boards also using MRC, and remove the need for any
mapping at all for the rest.
Change-Id: I3d79b33bac742faa9bd4fc9852aff73fe326de4e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Change-Id: I5e67e370d4eb8fe28227843bbca34db06ad84b26
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82786
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit b3db3abd6311924930f3250c9f9fc3157fbbf7da.
Reason for revert: `Wcalloc-transposed-args` is new command option came with GCC-14. older versions will not support it.
Change-Id: I74ef8de1f7d38e1e0519c3b41e79fd9b11d8e16f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82759
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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<stdio.h> header is used for input/output operations (such as printf,
scanf, fopen, etc.). Although some input/output functions can manipulate
strings, they do not need to directly include <string.h> because they
are declared independently.
Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GCC-14 documentation says "The first argument to calloc is documented to
be number of elements in array, while the second argument is size of
each element, so calloc(n, sizeof (int)) is preferred over
calloc(sizeof(int), n)."
Change-Id: I77b6f4d2eda487b087ba5665b588999633c33e8d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82658
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allowing access to change GPIO configuration from ACPI is asking
for trouble. Kill it while nobody cares (yet).
Access to mainpulate and blink GPIOs is maintained.
Change-Id: Id80a7e2f815a58750623c133bb30e5ed84a6e2ed
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Break out the individual bits of GPIO blink register as was done
for GPIO level register. An upcoming patch will use this.
Change-Id: I6f4749f60a9d569deba4b31f09f07a1321dabf4a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81922
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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ibexpeak has no USB 3 capabilities.
They were kept briefly when its devicetree structure was split from
bd82x6x in commit ab4de83f4330 ("sb/intel/ibexpeak: Sever bd82x6x
source dependency") to verify correctness. With that done, they
can go.
Change-Id: I6b847e1532d2e84a7b408a8858c8613b322d0373
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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It shares southbridge devicetree definition with bd82x6x, causing
changes made there to break builds for boards with this PCH. Give
ibexpeak its own copy.
TEST=abuild tested with lenovo/t410, lenovo/x201, packardbell/ms2290. Timeless binary did not change for all.
Change-Id: I08229ca658bd9c360b6be6137d882d319041b730
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81889
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Program the AER capability header register in a single write because
it's write-once. In addition, only PCH-LP supports L1 sub-states, so
only report the L1 sub-state capability on PCH-LP. This follows what
Lynx Point PCH reference code version 1.9.1 does.
Change-Id: I08bd107eec7a3b2f1701c4657ae104e0818ae035
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57503
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Lynx Point PCH reference code version 1.9.1 masks the upper 4 bits of
the PCIe root port register at offset 0xf5.
Change-Id: I9529ad88d34a5cb4a09843e3165f3a70c5ea22e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57502
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Lynx Point PCH reference code version 1.9.1 programs the larger L1 exit
latency when ASPM is enabled. Document 535127 (BDW PCH-LP BS) also does
the same. Correct the condition accordingly. On Lynx Point, also remove
a now-redundant write to the LCAP register (offset 0x4c).
Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57501
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Found by inteltool on HP Pro 3500 Series running vendor firmware version
8.14 Rev.A.
Change-Id: I156787e533c2605e7440548a2d3bf711bb1af5d7
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81427
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Lynx Point PCH reference code version 1.9.1 checks bit 29 to detect ASPM
on PCH-LP root port #6, not bit 28. Document 535127 (BDW PCH-LP BS) also
uses bit 29 for root port #6. Correct the bit used in the check, as well
as the surrounding comments.
Change-Id: Ie4bd7cbbfc151762f29eab1326567f987b25ab19
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57500
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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<device/pci.h> is supposed to provide <device/pci_{def,type}.h>
Change-Id: Ia645b8dba8c688187a25916f508593f333821f88
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81831
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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<device/device.h> is supposed to provide <device/{path,resource}.h>
Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: Icd00f30a96c53f70babdcb8a77c4b6c2868619d8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I40e2e5a786499abbe2fce63d6e0f1ac1e780ab51
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Use uintptr_t for the IOAPIC base parameter of the various IOAPIC-
related functions to avoid needing type casts in the callers. This also
allows dropping the VIO_APIC_VADDR define and consistently use the
IO_APIC_ADDR define instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I912943e923ff092708e90138caa5e1daf269a69f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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Change-Id: Ie63499a4b432803a78af1c52d49e34cf1653ba17
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80589
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the local IOAPIC ID variable is initialized as 2 and never changed
afterwards, so make it const to make this more obvious.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1f19cc43b44a938758a43346f4fa75f8ed39ddea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80349
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch moves the IP checksum algorithm into commonlib to prepare for
it being shared with libpayload. The current implementation is ancient
and pretty hard to read (and does some unnecessary questionable things
like the type-punning stuff which leads to suboptimal code generation),
so this reimplements it from scratch (that also helps with the
licensing).
This algorithm is prepared to take in a pre-calculated "wide" checksum
in a machine-register-sized data type which is then narrowed down to 16
bits (see RFC 1071 for why that's valid). This isn't used yet (and the
code will get optimized out), but will be used later in this patch
series for architecture-specific optimization.
Change-Id: Ic04c714c00439a17fc04a8a6e730cc2aa19b8e68
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80251
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
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This renames bus to upstream and link_list to downstream.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Macros can be confusing on their own; hiding commas make things worse.
This can sometimes be downright misleading. A "good" example would be
the code in soc/intel/xeon_sp/spr/chip.c:
CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev,
This appears as CHIP_NAME() being some struct when in fact these are
defining 2 separate members of the same struct.
It was decided to remove this macro altogether, as it does not do
anything special and incurs a maintenance burden.
Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Move the definition of the TCO registers used in most boards to a
separate file and use it consistently. Do not unify TCO for older
incompatible platforms.
BUG=b:314260167
TEST=none
Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6
Signed-off-by: Marek Maslanka <mmaslanka@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
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The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic80d27a963da8eddc3d1f0d9a3d59763028d4ed0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80075
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Work around a romstage restriction. Globals (or static variables) cannot
be initialized to a non-zero value because there's no data section. Note
that the revision ID for stepping A0 is zero, so `pch_silicon_revision`
will no longer use the cached value for this PCH stepping. Since it is a
pre-production stepping, it is most likely not used anywhere anymore.
Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Change-Id: I867451ae3d6d37033c9e0e57a4d7fd4a06dedbef
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77738
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
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Program SATA IOBP and enable clock gating after port enable
bits have been written.
The same registers are already set for DMI and PCIe.
TEST: Lenovo X220 still boots over SATA.
Change-Id: I50970117ddcf8d39796426a19c1a6b57e5b1e690
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79146
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Describe the USB 'current' settings based on MRC.bin that converts
the USB trace length to a predefined register value.
MRC.bin decides which setting to use based on the PC type, mobile
or desktop, and the trace length.
Tested: Lenovo X220 still boots.
Change-Id: I79d35ca16818daec03ee7f464349a4c8ee0f78e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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According to BWG the USB current setting 0 should not be used for
desktop boards. As autoport defaults to 0 if the USB current doesn't
match one of the lookup table entries most of the desktop boards in
tree have such a setting. Print an error to alert users of such boards
to update the USB current settings.
Tested: Lenovo X220 still boots.
Change-Id: If76e9126b4aba8e16c1c91dece725aac12e1a7e9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78827
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia5e1ee683fa3d8d216ece26426e9870981ede2ba
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79932
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: If4ae9c800325f5de8f170f8922bacffad1c9bb20
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77532
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Identify PCH type by LPC device ID. This allows to identify
the PCH without including northbridge headers.
Tested: Lenovo X220 still boots.
Change-Id: Ic3e15c1d8d4b1d1012d6204cc65de92d91431fbe
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add and use defines for 6 series and 7 series PCH PCH IDs.
Change-Id: I4de37d5817766b9bc4f5c2d4d472d3c456b14b29
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79546
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This southbridge can route POST codes written to port 0x80 to either
LPC or PCI, but currently always route them to LPC. Change it so that
POST codes are routed to PCI if CONFIG(POST_DEVICE_PCI_PCIE) is
selected, LPC otherwise.
Rename the static function because POST codes no longer always go to
LPC.
Change-Id: I455d7aff27154d6821e262a21248e8c7306e2d61
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This updates all warnings currently being printed under the files_added
and build_complete targets to the show_notices target.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia14d790dd377f2892f047059b6d24e5b5c5ea823
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79423
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PCH identification functions and `pch_iobp_update` are used in multiple
stages. Move them out of `pch.c` to drop some ugly preprocessor usage.
Subsequent commits will use `pch_iobp_update` in romstage as well.
Change-Id: I8d33338a4f74fd03c8f99f8fcece99b63c28adab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79624
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the EHCI controllers in the PCH are always on the same device
functions, the device operations can be statically assigned in the
devicetree and there's no need to bind the EHCI device operations to the
PCI devices during runtime via a list of PCI IDs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I92ecc3607216fb2f31639db9628898c9ce81770d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79171
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Since the XHCI controller in the PCH is always on the same device
function, the device operations can be statically assigned in the
devicetree and there's no need to bind the XHCI device operations to the
PCI device during runtime via a list of PCI IDs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8685bec734415346a53330c9bd1aa82986995f1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79170
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Since the PCI bridge in the PCH is always on the same device function,
the device operations can be statically assigned in the devicetree and
there's no need to bind the PCI bridge device operations to the PCI
device during runtime via a list of PCI IDs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic9ca925a12e64c9a5b3bf295653bf032572ff29a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79169
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Since the SMBus controller in the PCH is always on the same device
function, the device operations can be statically assigned in the
devicetree and there's no need to bind the SMBus device operations to
the PCI device during runtime via a list of PCI IDs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3d3745ba5aefa30efbe705155d216aa7eadd26a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79168
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the LPC bridge in the PCH is always on the same device function,
the device operations can be statically assigned in the devicetree and
there's no need to bind the LPC bridge device operations to the PCI
device during runtime via a list of PCI IDs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I366226be4aba75b98e45e4832bfe129fac14dbfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Since the HD audio controller in the PCH are always on the same device
functions, the device operations can be statically assigned in the
devicetree and there's no need to bind the host bridge device operations
to the PCI device during runtime via a list of PCI IDs.
TEST=Lenovo X220 still boots to Linux and audio still works
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I9bbbe9f4490dc6fb21174d63d1c8906d69ea3ee0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79118
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the PCIe root ports in the PCH are always on the same device
functions, the device operations can be statically assigned in the
devicetree and there's no need to bind the host bridge device operations
to the PCI device during runtime via a list of PCI IDs.
TEST=Lenovo X220 still boots to Linux and all PCIe devices on PCH are
visible and working.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I05bfe8db88fd54415f320f32ea147636ca4e0df8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Rename AZALIA_PLUGIN_SUPPORT to AZALIA_HDA_CODEC_SUPPORT and add a help
text to this Kconfig option to clarify what this option is about.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I71e36869c6ebf77f43ca78f5e451aebfb59f1c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The write to register 0x42 has no effect as at this point all
of the bits are read-only. Drop the line.
Change-Id: I7293e6eaa2d0bac5efe8316029bdecb04a5586e9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78238
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Because integrated PCI devices are hidden in chip_ops
the PCI enumeration code never sees them.
When hiding static devices mark them as hidden so the
PCI enumeration no longer complains about them being
missing, even though they are present and were working
just fine.
Test: Disabled southbridge devices no longer appear in
"Leftover static devices:" log.
Change-Id: Iae70072a85b62a456102190a5f72f4d652ad6d5a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Warn when a device took longer than usual to appear.
Use the PDS bit to detect if a root port has a downstream
device connected and warn if enumeration failed.
Test: On Lenovo X220 all PCIe device are visible, thus the
added code path is never taken.
Change-Id: I86b498b89d672b239d9951e116dc3680030666a6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78229
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use defines instead of magic values.
Test: Lenovo X220 still boots and all PCIe devices are
still working.
Change-Id: Ie8fc7cc863017da07dd3ed37b487dae18de92b18
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78293
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Use pci_find_capability() and defines from pci_def.h
- Set the 'Hotplug Capable' bit and 'Hot Plug Surprise' bit in SLCAP
for hotplugable PCIe slots.
- Assign unique slot number and set power limit for PCIe root ports
that have a slot connected. For integrated devices clear slot number
and power limit.
Test: System still boots and all PCIe devices are working.
Change-Id: I03aeb0a1ff0041901acc20fe700d3f7995d22366
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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On ICH9 the SPI control register is not naturally aligned
and a word write might be split into smaller naturally aligned
I/O transactions.
As the first byte starts a new SPI transfer, replace the existing
word write with two byte writes and write the second byte first.
This is required for platforms that do not support unaligned
word I/O instructions and would start a SPI transfer while the
second byte hasn't reached the control register yet.
TEST: Virtual SPI controller on qemu 8.0 doesn't start a transfer
early.
Change-Id: Id05b1a080911b71b94ef781c6e26d98165f02f67
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Introduce pci_is_hotplugable is helper to find hotpluggable
PCIe devices.
Test: PCI express slot is still marked as the only hotpluggable
PCIe root port.
Change-Id: I25aae540ff2ffa3ec5b93ed9caa838b4e50048d2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78227
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow the PCH BIOS spec more closely by porting the broadwell
and braswell PCIe downstream device detection. To safe power
disable PCIe root ports that have no downstream device connected.
By setting the FLAGS_SLOT bit in register PCI_EXP_FLAGS the
PCI_EXP_SLTSTA_PDS bit will be updated with in band device
detection from the PCIe PHY. While this is primarly used for PCIe
hot-plug detection, it is more reliable than probing for downstream
devices by reading DID/VID PCI registers.
The FLAGS_SLOT bit should stay cleared for integrated devices,
as those are known to be present, but to simplify the code all
PCIe ports will have the FLAGS_SLOT bit set. There currently
used devicetrees might also be lacking integrated devices on
the PCH root ports...
The SLOTCAP field must be updated by BIOS when the FLAGS_SLOT
is set, but it shouldn't be filled for integrated devices. Until
now the SLOTCAP field has always been populated and it never
was a problem.
- Set FLAGS_SLOT "Slot Implemented" bit early.
- Read bit PCI_EXP_SLTSTA_PDS to detect connected downstream
devices as done on braswell.
- Disable unused PCIe slots that are not hotplugable.
- Set BIT26 in register 0x338 and wait for bits in register 0x328
to clear as done on broadwell.
Test: Tested on Lenovo X220. Unused root ports are disabled and port
that are in used or marked hot-plug are kept enabled.
Change-Id: I8ccfcab2e0e4faba8322755a4f8c2108d9b007ac
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78226
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PCH BIOS spec says that BIOS must clear BIT26 in register 0x338
in PEI, as done on lynxpoint.
Copy and adapt the lynxpoint code to do the same on bd82x6x.
Add special case for UM77 chipset, which only has 4 PCIe ports.
Test: System still boots and all PCIe ports are fully working.
Change-Id: I865818c0c22194fffcb2bbdf8c43737b0dce2307
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ic3e9570c110d8cded8c00e74fff29cc3a711582e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Change-Id: I2e8eb3632c93b4449f108cb690f9bfd8e1ea3776
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77767
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Backport commit cf544ac (broadwell: Remove XHCI workarounds on WPT).
Newer Lynxpoint reference code shows LPT-H also uses these workarounds.
Also, add the `ISWP` object (Name or Method) to test for WildcatPoint.
Change-Id: I76bc07e585e8af292c7316442760d1cfabf1e9c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46960
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the commonlib, console, northbridge, security, and
southbridge directories that don't already have an SPDX license line
at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I02804a10d0b0355e41271a035613d9f3dfb122f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Debug messages shown during IDE initialization are streamlined as
follows:
"Primary IDE interface" (and similar) are shortened to
"Primary interface".
We don't need to see "IDE" twice as messages are already prefixed.
Refactor "IDE: (Primary) IDE interface: (on)" into
"IDE: (Primary interface): (on)" to allow compiler to deduplicate
component strings, also used later in messages re UDMA/33.
This reduces uncompressed string size by 32 bytes and allows ramstage
to compress a wee bit better.
Change-Id: I16f5c2b3775c5a73b83d83817d7075e944089a12
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73331
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Once platform code has filled in the (legacy) ACPI PM register
map, added function will fill in the extended entries in FADT.
TEST=samsung/lumpy and amd/mandolin FADT stays unchanged.
Change-Id: I90925fce35458cf5480bfefc7cdddebd41b42058
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Remove dummy SOUTH_BRIDGE_OPTIONS.
Change-Id: Ic2f10ef03844ff55addfa27035b54971ac41dbc9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Remove dummy SOUTH_BRIDGE_OPTIONS.
Change-Id: Ifce7965040d96486ee8de2fba2ead9c54ee9a9f9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76948
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: If31cbc5ae184c4eb66011666c1bb655fa16afba0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I7e2018dbccead15fcd84e34df8207120d3a0c57c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64303
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
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The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \
src/commonlib/include/commonlib/console/post_codes.h;
myArray=`grep -e "^#define POSTCODE_" \
src/commonlib/include/commonlib/console/post_codes.h | \
grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`;
for str in ${myArray[@]}; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r POST_$splitstr src | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
grep -r "POST_$splitstr" util/cbfstool | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
done
Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Signed-off-by: lilacious <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This is needed to support 9-series PCH-H (e.g. Z97) and Broadwell
non-ULT CPUs (for which more magic is required).
Tested on Asrock Z97 Extreme6: Boots, but ME has to be disabled so that
the system remains on after 30 seconds. Apparently, something Broadwell
MRC.bin does results in the ME being unhappy, as there is no such issue
when not using MRC.bin at all (native RAM init). S3 resume is working.
Change-Id: I7b33660099fa75c5ad46aeeda17b1215729f96c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Locate it with all the other PM IO registers.
Change-Id: I779b2e313c9d8370c66c4adb4f6f4d4cf5b4e7dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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By ACPI specification, those follow GPE0_EN bits in the register space.
Use sizeof() to replace the 2/4 offset previously used.
Change-Id: I27ada0b19b2cf5e8eca71f48bf103dcab1b3cc11
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74514
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Change-Id: I27a610255e5680be1b507d45c6695cf9419ee052
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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No longer needed, this was used with old SMM relocate code.
Change-Id: I7c913e10eb965419c7d2ddede744f8140a5b7976
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I7655de5a8fcd5ac5c820938059bbb8b1ad877db7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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To select COMMON_SMM should not imply COMMON_PMBASE, it's
really a depencency. Select them both explicitly for i82801dx.
Change-Id: I387ade9cfd38b6555ed9e37c1b9178a6da2d7260
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This allows mainboards to override available sleep states at runtime.
This is done by adding a IntObj in SSDT that DSDT consumes to override
the available _Sx states.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic21830c1ef9c183b1e3005cc1f8b7daf7e9ea998
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74762
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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FADT duty_width/duty_offset fields, together with P_CNT (previously
P_BLK) IO address are provided with _PTC entry.
FADT p_lvl2/3_lat fields had values that disabled C2/C3 state
transitions so _CST entries are not required.
Change-Id: I629cd0793f6a64e955e197400efaa7d9d898e775
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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I forgot to remove these in commit 0fe36db154eb ("ACPI: Make FADT
entries for SMI architectural").
Change-Id: Ib1bc1dad6053ddb0454d4510917fd2bcf0901f35
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74811
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY
that points to same offset. Since the century field inside
RTC falls within the NVRAM space, and could interfere with
OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY.
There were no reference for the use of offset 0x48 for century.
Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I80aa71b813ab8e50801a66556d45ff66804ad349
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74600
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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In order to make supported sleep states a runtime configuration option
use a variable. A follow-up patch will implement updating this variable
based on an SSDT generated IntObj.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I6910c2c75e668e6f75a6f431813edeb59d52dd93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Since skylake Intel hardware does not support this sleep state. Trying
to enter S1 by having the OS enter sleep results in a system hang on at
least Alder lake (prodrive/atlas).
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC is a good proxy whether devices
support 'skylake style' PMC PCI device for ACPI registers.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic9e19410696240755e8714db53a0525284f3a2da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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For uni-processor platforms, with SMP=n or MAX_CPUS=1,
neither the LAPIC or IOAPIC MADT entries are added.
Change-Id: I8777f4e3b37fe7b564189c6bf48e3988026b2361
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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IRQ override from IRQ #0 to GSI #2 is changed from
MP_BUS_EISA to MP_BUS_ISA.
Change-Id: I115df037fd79e120b04e6aff9e53f963f045b997
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change IRQ #0 to GSI #2 override to positive edge trigger from
the bus ISA default (positive edge).
Change-Id: Iab3d38da9610ede1d338440b4a8ec0f1537c17e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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i82801gx, i82801ix, i82801jx:
Maintain IRQ #0 to GSI #2 override as positive edge trigger.
ibexpeak, emulation/qemu-q35:
Change IRQ #0 to GSI #2 override to positive edge trigger from
the bus ISA default (positive edge).
Change-Id: Ia8a04daf3a79d9f2f4801dc85e4975278e30dc8a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Platform needs to implement this to provide information about SCI IRQ
pin and polarity, to be used for filling in ACPI FADT and MADT entries.
Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: Ibe5d84c8fbff79cc73b01eee0980cbed71ceb506
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Fix after 'commit 69a13964ea6c ("sb,soc/amd,intel: Add and use
ACPI_COMMON_MADT_LAPIC")' broke interrupt delivery in kernel.
Apparently combination of LAPIC without IOAPIC is too rare
to be well supported.
Change-Id: I5e2fbf358cf644665b897afb0a9404abb5ca1df2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74472
Reviewed-by: Branden Waldner <scruffy99@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I7d0718b5d2e0dd16eb90f63dd9d33329a2d808ba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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C0 clock throttling was disabled, no need to add _PTC.
C2/C3 latency values were copy-paste from different CPUs.
TBD: Check IO-trap
Change-Id: Ia0e35e28f0df8b0f8fc58f70c7d792487ee4f7f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74439
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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After the obsoletion of Processor() it is necessary to provide
_PTC package to define P_CNT IO address for clock throttling.
The platforms touched here already emit empty _PTC to disable
clock throttling.
Change-Id: I0e84c8ccd2772c9b3d61f71b74324c8d28f4eefe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74438
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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