| Age | Commit message (Collapse) | Author |
|---|
|
There's an occasional issue on machines which use CMOS for their
vbnv storage. The machine that just powers up from complete G3
would have had their RTC rail not held up. The contents of vbnv
in CMOS could pass the crc8 though the values could be bad. In
order to fix this introduce two functions:
1. vbnv_init_cmos()
2. vbnv_cmos_failed()
At the start of vboot the CMOS is queried for failure. If there
is a failure indicated then the vbnv data is restored from flash
backup or reset to known values when there is no flash backup.
BUG=b:63054105
Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to early_pch_common.c and
add a helper function to determine if failure occurred.
BUG=b:63054105
Change-Id: I710d99551cfb6455244f66b47fcbecc790ae770f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.
BUG=b:63054105
Change-Id: I368c31b9935c0fa9e8a1be416435dd76f44ec1ec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
me_cleaner now allows setting a bit in the PCH straps - AltMeDisable
tells the ME to stop execution after BUP - disabling the 30 minute
watchdog - but also "breaking" the ME. The ME reports opmode = 2.
This means the ME will not respond when we wait for an acknowledgement
about the DRAM being ready. The current code waits 5 seconds for a
response, that in this case, never comes.
If the ME is reporting opmode 2, don't delay or wait for a response
from the ME.
Tested on my X220, this patch fixed the five seconds before the payload
executed. Verified using the timestamp patch.
Change-Id: Ifdda6b2dbb8ae3a650be6d5df6c60475a3fa74aa
Signed-off-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-on: https://review.coreboot.org/21466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
There's no reason to mutate the struct device when determining
the ACPI name for a device. Adjust the function pointer
signature and the respective implementations to use const
struct device.
Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Add a timestamp before and after waiting for the ME to acknowledge the
DRAM being ready.
This allows easier debugging during use of me_cleaner and/or alternate
ME images.
Change-Id: Ie228e12a75d373b4f406b3595e1fb1aab41aa5df
Signed-off-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-on: https://review.coreboot.org/21465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I1a84b4451efe25c1c3b0ce33ddbcb6ed06c29f9e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Failed to build with DEBUG_SMBUS=y, slave_bytes is
not initialized until inb().
Change-Id: Ia53717756ed74bc797a9529e36fc6965d6872101
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21470
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: Ifb1a1eff71968f31af9004ff00717f202d3ec29e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Coding style, sync implementation with SMBus counterpart.
Change-Id: I75f24e2308de945fc03289636ae914bb87070838
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
I forgot to push these changes before merging commit
1b04aa2 sb/intel/common: Fix SMBus block commands
Change-Id: I7217f8c0cc78f2161faf31a4c49e3e9515026d15
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
__packed has been introduced in commit 6a00113de8
("Rename __attribute__((packed)) --> __packed"). Use it.
Change-Id: Ifd33129ae4fbe14c26ceeaaa88832ef994a32dfb
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
On platforms with a PCH, some registers within host bridge should be
locked down on each normal boot path (done by either coreboot or
payload) and S3 resume (always done by coreboot).
A function to perform such locking is implemented in src/northbridge/
intel/*/finalize.c, and is designed as the handler of an #SMI triggered
with outb(APM_CNT_FINALIZE, APM_CNT), but currently this #SMI is only
triggered during s3 resume, and not on normal boot path. This problem
has beed discussed in
https://mail.coreboot.org/pipermail/coreboot/2017-August/084924.html .
This time, an option "INTEL_CHIPSET_LOCKDOWN" within src/southbridge/
intel/common/Kconfig is added to control the actual locking, which
depends on several compatibility flags, including
"HAVE_INTEL_CHIPSET_LOCKDOWN".
In this commit, "ibexpeak", "bd82x6x", "fsp_bd82x6x", and "lynxpoint"
have the flag "HAVE_INTEL_CHIPSET_LOCKDOWN" selected.
The change is only well tested on Sandy Bridge, my Lenovo x230.
Change-Id: I43d4142291c8737b29738c41e8c484328b297b55
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
"pcie_port_coalesce" will cause pcie being remapped under certain
conditions, but flags within "pcie_hotplug_map" should be updated
along with ports.
Test on my lenovo t430s.
Change-Id: I28c4eaf82fb52fe793dfa2f824f14686b80951ad
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21178
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Rename register to match recent intel models.
Required for Lenovo H8 to operate on all generations.
Change-Id: I48a869adb1da2e33156968c4b7597edf99902c1a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Relevant changes (commit 2e8761e):
* Add an option to truncate the ME image file
* Add full support for Skylake (ME 11) and following, including
modules removal, truncation informations and partition
relocation
* Add two options to generate a shrinked ME image file and the
corresponding descriptor with a modified flash layout
* Update README.md
* Bug fixes
Also add a link to the usage guide in the Kconfig help.
Change-Id: I690c5d558139f64f38babf3c0988b53834ba8b37
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/20915
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
Clear LAST_BYTE flag at beginning of block commands.
For reads, slave device determines in the message format how
many bytes it has to transfer out, host firmware only dictates
the maximum buffer length. Return SMBUS_ERROR if only
partial message was received.
For writes, return SMBUS_ERROR if length > 32.
For writes, fix off-by-one error reading memory one
byte past the buffer end.
Change-Id: If9e5d24255a0a03039b52d2863bc278d0eefc311
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
SMM relocation code overwrite low memory owned by OS.
Change-Id: Ifa3d28bed3d3db65b0707bde62ae2b424a231f1a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19405
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Setting up default BARs and DMI init code is done in northbridge
code.
Change-Id: I6cfa3018ca7f5ef351415c4ec6e178ade353f7a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Always sanity check for EHCI class device and move
PCI function power enablement up.
Change-Id: I1eebe813fbb420738af2d572178213fc660f392a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
There is assumption of static EHCI_BAR_INDEX, try to
clean it up by bringing BAR programming at one spot.
Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Taking ownership is handled with DBGP_OWNER within
usbdebug driver code.
Change-Id: Ia5da10d385cda1b4968f812967ea8a54d7e3c974
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Guckian <david.guckian@intel.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: I76bf1ed392d3d18059792106fc482d2259a3f084
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Uses common hardware access functions to make smbus block read and
write available in romstage.
Those are needed to reconfigure the clockgen on smbus offset 0x69,
which is sometimes needed for things like CPU C-states or analog
display out to work properly.
Change-Id: I0a06178d2474ce65972de157cb437b42f3354da0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
All Intel southbridges implement the same SMBus functions.
This patch replaces all these similar and mostly identical
implementations with a common file.
This also makes i2c block read available to all those southbridges.
If the northbridge has to read a lot of SPD bytes sequentially, using
this function can reduce the time being spent to read SPD five-fold.
Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
IOBP (I/O Buffer Programming) is an interface (indirect addresses space)
in the RCBA that is used to configure the high speed serial lanes on the
PCH, that are used for PCIe, USB3 and SATA.
This patch replaces the offsets in RCBA with the defines from pch.h, gives
the access functions and their parameters useful names and replaces two
magic addresses in IOBP space with their defines.
Change-Id: I91a828ed076ca10733b47db876fabf5adaa63638
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/16214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The save_timestamp_to_cmos code was used at Sage before the early
cbmem was available. Update it to use the standard timestamp calls,
based on the rangeley implementation.
Change-Id: I9a3a6609bdc8d03c4b86951daa1cafddd9c1332e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: If8e82a291f666d5f310422b100f02d5df17ab74e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Interrupt 11 is not used by legacy devices and so can always be used
for PCI interrupts. Full legacy IRQ routing is complicated and hard to
get right.
Change-Id: I6c718f4b9fb91ffcc4a136120581a4fcd7ec7231
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Make sure to set only one bit instead of arbitrary bits set in argument.
Change-Id: I39426193d15d8581f79bc2a45c0edb53b19a2cd3
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Function copied from i82801gx with offsets fixed for i82801lx.
Change-Id: Ib420c69470c3190cc1eac234ce68a18382fbc04a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
File copied from i82801gx.
Change-Id: I107087b6448f18b6a5ae21c2ae0392c057dd23b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Adapted from i82801gx.
Change-Id: I9108a45135908b7c4e74e9df3bb8f89f55893299
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This chipset was just added and had a few places that needed to be
fixed.
Change-Id: Ief048c4876c5a2cb538c9cb4b295aba46a4fff62
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20684
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I878960e7e0f992426382ca717b8b42787f01ebc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Also unify __attribute__ ((..)) to __attribute__((..)) and
handle ((__packed__)) like ((packed))
Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Fix undefined behavior found by clang's -Wshift-sign-overflow, grep,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.
Change-Id: I10db2566199200ceb3068721cfb35eadb2be1f68
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: Ic8b0e6404a3f90312f7d2d3b6c367b0a1d9ec6e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
Change-Id: Ib3a69f45b48c19c61b12a992b23dad1693bf5f9e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I1b2a16e8eb70819c72efd50f30a57f3687f31bb5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I8ea8fdb031c09aac9ed4a0705c3204f87aadb565
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Fixes report found by undefined behavior sanitizer. Dereferencing a
pointer that is not aligned to the size of access is undefined behavior.
Change-Id: Ia3c95e36e8b7f88ed69d5339e299c40934cb87da
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Fix reports found by undefined behavior sanitizer. Left shifting an int
where the right operand is >= the width of the type is undefined. Add
UL suffix since it's safe for unsigned types.
Change-Id: I755b3c80a8d1b6cb6b6e5f411c6691e5dd17c266
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Fill in acpi_name to return proper ACPI names.
To be used with SSDT generators.
The ACPI names have to match those already used in ASL code.
By providing the ACPI name it can be retrieved by the
acpi_device_name() method and doesn't need to be hardcoded in
SSDT generators any more.
HDEF is defined in sb/intel/bd82x6x/acpi/audio.asl.
LPCB is defined in sb/intel/bd82x6x/acpi/lpc.asl.
RP0* is defined in sb/intel/bd82x6x/acpi/pcie.asl.
SATA is defined in sb/intel/bd82x6x/acpi/sata.asl.
SBUS is defined in sb/intel/bd82x6x/acpi/smbus.asl.
EHC? is defined in sb/intel/bd82x6x/acpi/usb.asl.
XHC is defined in sb/intel/bd82x6x/acpi/usb.asl.
Change-Id: I08611b11c694ee5034bca11cb321915d5c73c2f6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Add a GNVS variable to store trackpad IRQ for google/parrot, so
that both SNB and IVB variants can be built with the same config
Change-Id: I232da4077e3400b8ef2520dc33fd770c731b7ec3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
While building poppy board, build failed with following error message:
Writing new image to build/coreboot.pre.new
mv build/coreboot.pre.new build/coreboot.pre
util/me_cleaner/me_cleaner.py -c build/coreboot.pre > /dev/null
This image does not contains a ME/TXE firmware NR = 0)
make: *** [src/southbridge/intel/common/firmware/Makefile.inc:55:
add_intel_firmware] Error 1
Hence keeping CHECK_ME unset by default.
TEST=Succesfully built coreboot for Poppy & booted to OS.
Change-Id: Ib3186498c8da307b686c06c3828e24acbc7f2d17
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/19257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This reverts commit f4835a85c0e851d13bcfed53a23f495caeefe8e2. It
completely ignores port coalescing and breaks enumeration in many
cases. The code reused to disable and hide the root ports was never
meant to be called that way.
The same effect of power saving can likely be achieved by clock
gating unused ports after enumeration without further, error-prone
function hiding.
Change-Id: I90d8b9236004f0c42d5a2b6bbd39f6dea07bd3d1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
There are many good reasons why we may want to run some sort of generic
callback before we're executing a reset. Unfortunateley, that is really
hard right now: code that wants to reset simply calls the hard_reset()
function (or one of its ill-differentiated cousins) which is directly
implemented by a myriad of different mainboards, northbridges, SoCs,
etc. More recent x86 SoCs have tried to solve the problem in their own
little corner of soc/intel/common, but it's really something that would
benefit all of coreboot.
This patch expands the concept onto all boards: hard_reset() and friends
get implemented in a generic location where they can run hooks before
calling the platform-specific implementation that is now called
do_hard_reset(). The existing Intel reset_prepare() gets generalized as
soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now
easily be added later if necessary). We will also use this central point
to ensure all platforms flush their cache before reset, which is
generally useful for all cases where we're trying to persist information
in RAM across reboots (like the new persistent CBMEM console does).
Also remove cpu_reset() completely since it's not used anywhere and
doesn't seem very useful compared to the others.
Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19789
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Disable unused bridges that are not marked as hot-plugable.
Reduces idle power consumtion by ~200mWatt for each port.
Tested on Lenovo T430.
Change-Id: I6ee5e5f33824acdbca0f6ed28e90beab7fe10002
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19818
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
Use register name instead of magic value.
Change-Id: I4f2f3f196c12489613333ab9f6098443edda927f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Add device/address stubs for XHCI USB ports 7, 10-13.
Stub data will be supplemented by board-specific info
added in subsequent commits.
Change-Id: I7d2f93351435cccd62e8fe4d95ad3467aa09de69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19965
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
Change-Id: If63d5637a0469eeace0d935cca961e8d04fdfb1a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
Change-Id: Ib83660d6548112ceb6c75a31e5ce6c4a6041ccfb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I23c1108c85532b7346ff7e0adb0ac90dbf2bb2cc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
Add support to the Intel common firmware Kconfig and Makefile.inc to
allow the embedded controller (EC) blob to be added to the final
binary through ifdtool.
TEST=Add ec.bin and enable in config, build is successful.
Change-Id: Ib14732b4d263dde4770bf26b055c005de2540338
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
Lock CF9GR as documented in "100-series-chipset-datasheet-vol-2.pdf"
Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Only board using this code was tyan s2735 which was removed in
f76de841f1 "[REMOVAL] tyan/s2735"
Change-Id: I03a101adc1eedfa9669e0b44c54c2c6fa08bd5f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Define a new spi_flash_ops structure, move all spi flash operations to
this structure and add a pointer to this structure in struct spi_flash.
BUG=b:38330715
Change-Id: I550cc4556fc4b63ebc174a7e2fde42251fe56052
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
1. Rename __spi_flash_probe to spi_flash_generic_probe and export it
so that drivers can use it outside spi_flash.c.
2. Make southbridge intel spi driver use spi_flash_generic_probe if
spi_is_multichip returns 0.
3. Add spi_flash_probe to spi_ctrlr structure to allow platforms to
provide specialized probe functions. With this change, the specialized
spi flash probe functions are now associated with a particular spi
ctrlr structure and no longer disconnected from the spi controller.
BUG=b:38330715
Change-Id: I35f3bd8ddc5e71515df3ef0c1c4b1a68ee56bf4b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Pointer to spi_slave structure can be passed in as const to spi flash
probe functions since the probe functions do not need to modify the
slave properties.
BUG=b:38330715
Change-Id: I956ee777c62dbb811fd6ce2aeb6ae090e1892acd
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19707
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Instead of making all SPI drivers allocate space for a spi_flash
structure and fill it in, udpate the API to allow callers to pass in a
spi_flash structure that can be filled by the flash drivers as
required. This also cleans up the interface so that the callers can
maintain and free the space for spi_flash structure as required.
BUG=b:38330715
Change-Id: If6f1b403731466525c4690777d9b32ce778eb563
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
spi_crop_chunk is a property of the SPI controller since it depends
upon the maximum transfer size that is supported by the
controller. Also, it is possible to implement this within spi-generic
layer by obtaining following parameters from the controller:
1. max_xfer_size: Maximum transfer size supported by the controller
(Size of 0 indicates invalid size, and unlimited transfer size is
indicated by UINT32_MAX.)
2. deduct_cmd_len: Whether cmd_len needs to be deducted from the
max_xfer_size to determine max data size that can be
transferred. (This is used by the amd boards.)
Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19386
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: coreboot org <coreboot.org@gmail.com>
|
|
Use defines instead of magic values.
No functional change.
Change-Id: Idc90f254d7713f96a6e8b0389e34d860f461d9d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Use register name instead of hex values.
No functional change.
Change-Id: I08fc8435f29ab87a0534946b0e0c43231919785d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
Change-Id: I97c3402ac055991350732e55b0dda042b426c080
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19310
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
Change-Id: I76b31fe5fd19b50b82f57748558fb04408e0fd23
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19309
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
Change-Id: Ie5d93117ee8bd8d15085aedbfa7358dfcf5f0045
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19307
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Once the PCI command register is written the bridge forwards
future IO and memory regions, as programmed in the respective base
and limit registers, to the secondary PCI bus.
Since the LPC function claims the resources for IOAPIC, ROM and
low IO (0x0-0xfff) in its read_resources() call, the PCI-to-PCI
configuration will not overlap those regions and does not hide
the resources mentioned in the original comment.
The bridge was disable in the following commit [1]
commit a8e1168064b34b46494b58480411a11bc98340f6
Author: Stefan Reinauer <stepan@coresystems.de>
Date: Wed Mar 11 14:54:18 2009 +0000
This patch contains some significant updates to the i82801gx component and will
be required for a series of later patches. Roughly it contains:
but unfortunately it was not noted which system this caused
problems with.
[1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=a8e1168064b34b46494b58480411a11bc98340f6
Change-Id: I75128d83a344f4a0e09a3ea623c7f92a016ebfb9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/2706
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Using i2c_block_read speeds up reading SPD four to fivefold compared
to sequential byte read.
TESTED on Intel D945GCLF.
Change-Id: I6d768a2ba128329168f26445a4fca6921c0c8642
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18927
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: Iddc67e7c126ce19429afc24b021e385353564cb8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18705
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Ensure that the provided ME/TXE firmware is valid, using the
check capabilities of me_cleaner.
me_cleaner checks that the fundamental partition is available and
it has a correct signature. The checks performed by me_cleaner
aren't exhaustive, but they should find at least whether the user
has provided an empty or corrupted firmware.
me_cleaner has been tested on all the ME (6-11.6) and TXE (1-3)
firmwares available here [1], and it hasn't reported any false
positive.
[1] http://www.win-raid.com/t832f39-Intel-Engine-Firmware-Repositories.html
Change-Id: Ie6ea3b4e637dca4097b9377bd0507e84c4e8f687
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18768
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
Once the PCI command register is written the bridge forwards
future IO and memory regions, as programmed in the respective base
and limit registers, to the secondary PCI bus.
It was previously argumented this is copy-paste and never known
to be required for these more recent platforms:
https://review.coreboot.org/#/c/2706/
Change-Id: Ic8911500a30bc83587af8d4b393b66783fa52e18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18330
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Setting both bits 27 and 7 of PCH register PMSYNC_CFG (PMSYNC
Configuration; offset 0x33c8) causes pre-OS display init to fail
on HSW-U/Lynxpoint and BDW-U ChromeOS devices when the VBIOS/GOP
driver is run after the register is set. A re-examination of
Intel's reference code reveals that bit 7 should be set for the
LP PCH, and bit 27 for non-LP, but not both simultaneously.
The previous workaround was to disable the entire power optimizer
section via a Kconfig option, which isn't ideal.
Test: unset bit 27 of PMSYNC_CFG and boot google/lulu,
observe functional pre-OS video output
Change-Id: I446e169d23dd446710a1648f0a9b9599568b80aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18385
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
We've been able to narrow down the problem to a single register/
single bit, so revert this commit and address the problem in a
follow-on commit.
This reverts commit 0f2025da0fd4dce6b951b4c4b97c9370ca7d66db.
Change-Id: I780f9ea2976dd223aaa3e060aef6e1af8012c346
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18384
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The apollolake boards don't have an me.bin proper, but they still have
descriptor regions which need to be locked down. Therefore, remove the
restriction of HAVE_ME_BIN from LOCK_MANAGEMENT_ENGINE.
BUG=chrome-os-partner:62177
TEST=For apollolake one can select LOCK_MANAGEMENT_ENGINE.
Change-Id: I73aab3a604ec25cd56d760bf76cc21c5a298799e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18304
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The me_cleaner option is available on multiple platforms:
* Sandy and Ivy Bridge (well tested by multiple users).
* Skylake and Braswell (tested).
* Haswell, Broadwell and Bay Trail (untested).
The untested platforms have been included anyways because all the
firmwares are very similar and Intel ME/TXE probably behaves in the
same way.
Change-Id: I46f461a1a7e058d57259f313142b00146f0196aa
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18206
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Other chips dump tco_status here if it wasn't handled, which makes
sense.
tco_sts can't be zero here, because the call would have already returned
if it were. Also, dump_tco_status wouldn't print anything if tco_sts
were zero.
This will still only print the debug information if DEBUG_SMI is
enabled in Kconfig, so in general, this change won't have much of an
effect on anything.
Found-by: Coverity Scan #1229598
Change-Id: Id2c69a16817ba18dfa051f514138fbc04a2f7bee
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18101
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This should always have been an and, not an or.
The only way this would happen is if no GPIOs were getting configured,
so we shouldn't ever have a NULL here, but if we did, GPIOs would
be randomly configured, which would have 'interesting' results.
Found-by: Coverity Scan #1229633 & 1229632
Change-Id: If123372658383f84279738e1186425beba3208ca
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18095
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Die if cbmem_add can't allocate memory for the hob pointer. This
shouldn't ever happen, but it's a reasonable check.
- fsp_broadwell_de already had a check, but it returned to someplace
inside the FSP. Just die instead.
Change-Id: Ieef8d6ab81aab0ec3d52b729e34566bb34ee0623
Found-by: Coverity Scan #1291162
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18092
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Default setting of southbridge assigned 1MiB of memory
for FWH ID 0, while 2MiB is commercially available.
Only remap IDs when large ROM is requested in case some
board uses multiple FWH parts.
Change-Id: I500425f42f755f911d84c6f94a9f3ab5a1ca0b51
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17918
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This is more consistent with newer Intel targets.
This a static struct so it is initialized to 0 by default.
To make it more readable:
* only setting to GPIO mode is made explicit;
* only pins in GPIO mode are either set to input or output since this
is ignored in native mode;
* only output pins are set high or low, since this is read-only on
input;
* blink is only operational on output pins, non-blink is not set
explicitly;
* invert is only operational on input pins, non-invert is not set
explicitly.
Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17639
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Write gpio level twice to make sure the level is set
after pins have been configred as GPIO and to minimize
glitches on newer hardware.
Required to set correct GPIO layout on T500.
Tested on T500.
Change-Id: I691e672c7cb52ca51a80fd29657ada7488db0d41
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18012
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
|
|
SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with
the ability to perform tx and rx of flash command and response at the
same time. Instead of introducing this notion at SPI flash driver layer,
clean up the interface to SPI used by flash.
Flash uses a command-response kind of communication. Thus, even though
SPI is duplex, flash command needs to be sent out on SPI bus and then
flash response should be received on the bus. Some specialized x86
flash controllers are capable of handling command and response in a
single transaction.
In order to support all the varied cases:
1. Add spi_xfer_vector that takes as input a vector of SPI operations
and calls back into SPI controller driver to process these operations.
2. In order to accomodate flash command-response model, use two vectors
while calling into spi_xfer_vector -- one with dout set to
non-NULL(command) and other with din set to non-NULL(response).
3. For specialized SPI flash controllers combine two successive vectors
if the transactions look like a command-response pair.
4. Provide helper functions for common cases like supporting only 2
vectors at a time, supporting n vectors at a time, default vector
operation to cycle through all SPI op vectors one by one.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17681
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Select this to provide menu in menuconfig to add flash
descriptor file. ME or GbE firmwares themselves are not
required, but integrated NIC MAC and SPI configuration
fields are still useful.
Change-Id: I14b86e2f38ec39924d2cbf0932d82f66ed356a03
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17805
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Scratchpad register was read too
late in ramstage so acpi_is_wakeup_s3() did not evaluate
correctly.
This fixes low memory corruption at 0x1000-0x102c and the lack
of coreboot tables (util/cbmem not working) after S3 resume.
This also fixes console log from reporting early in ramstage
"Normal boot" while on "S3 resume" path.
Change-Id: I2922a15a90d2f8272c3482579bdd96f8f33e9705
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17675
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Also fixes console log from reporting
early in ramstage "Normal boot" while on S3 resume path.
Change-Id: I4e2eabc59ff87b7ed40cfc9885bbe0256fe4a695
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17674
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The value for _size was not evaluated correctly if ramstage
is relocated, make the calculation runtime.
While touching it, move symbol declarations to header file.
Change-Id: I4402315945771acf1c86a81cac6d43f1fe99a2a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17784
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Make sure relocation code reaches DRAM before issuing any
SMIs. Snooping and cache coherency may have undefined
behaviour as CPUs do not have uniform MTRR layout yet.
Change-Id: I47a7d684e05ff8c1c2f1f6a5bf8c0bbc561d9eac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17712
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
We have kconfig.h auto-included and it pulls config.h too.
Change-Id: I665a0a168b0d4d3b8f3a27203827b542769988da
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17655
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
CHIPSEC found that the TCO_Lock was not set.
This is used to prevent changing the TCO_EN bit.
Change-Id: I42364dbef2511e656662566cf94591e76c6847ed
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Reviewed-on: https://review.coreboot.org/17351
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Doing PCI config operations via MMIO window by default is a
requirement, if supported by the platform. This means chipset
or CPU code must enable MMCONF operations early in bootblock
already, or before platform-specific romstage entry.
Platforms are allowed to have NO_MMCONF_SUPPORT only in the
case it is actually not implemented in the silicon.
Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17693
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17690
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.
All these platforms now have MMCONF_SUPPORT_DEFAULT.
I liked the style of code in pci_mmio_cfg.h more, and used those to
replace the ones in io.h.
Change-Id: Ib5e6a451866c95d1edb9060c7f94070830b90e92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17689
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.
All these platforms now have MMCONF_SUPPORT_DEFAULT.
Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17545
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.
All these platforms now have MMCONF_SUPPORT_DEFAULT.
Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17529
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Commit 36b81af (spi: Pass pointer to spi_slave structure in
spi_setup_slave) changes the way spi_setup_slave handles the spi_slave
structure. Instead of expecting spi controller drivers to maintain
spi_slave structure in CAR_GLOBAL/data section, caller is expected to
manage the spi_slave structure. This requires that spi_flash drivers
maintain spi_slave structure and flash probe function needs to make a
copy of the passed in spi_slave structure.
This change fixes the regression on Lenovo X230 and other mainboards.
Change-Id: I0ad971eecaf3bfe301e9f95badc043193cc27cab
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17728
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Iru Cai <mytbk920423@gmail.com>
|
|
1. Define a new structure spi_ctrlr that allows platforms to define
callbacks for spi operations (claim bus, release bus, transfer).
2. Add a new member (pointer to spi_ctrlr structure) in spi_slave
structure which will be initialized by call to spi_setup_slave.
3. Define spi_claim_bus, spi_release_bus and spi_xfer in spi-generic.c
which will make appropriate calls to ctrlr functions.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: Icb2326e3aab1e8f4bef53f553f82b3836358c55e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17684
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
