coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2018-06-09	sb/intel/lynxpoint: Get rid of device_t	Elyes HAOUAS
2017-07-10	southbridge/intel/lynxpoint: Fix undefined behavior	Ryan Salsamendi
2017-07-02	southbridge/intel/lynxpoint: Fix undefined behavior	Ryan Salsamendi
2016-08-28	src/southbridge: Add required space before opening parenthesis '('	Elyes HAOUAS
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-02-15	x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer	Kevin Paul Herbert
2014-07-08	southbridge: Trivial - drop trailing blank lines at EOF	Edward O'Callaghan
2014-07-04	intel/lynxpoint: Add SATA DEVSLP disable option	Marc Jones
2013-12-21	lynxpoint: Add configuration option for SATA gen3 DTLE registers	Shawn Nematbakhsh
2013-03-21	lynxpoint: Change sata.c to get rid of #if	Duncan Laurie
2013-03-14	haswell: more ULT/LP support and minor tweaks	Duncan Laurie
2013-03-14	lynxpoint: Update device IDs and clock gating setup	Duncan Laurie
2013-03-14	haswell: Add initial support for Haswell platforms	Aaron Durbin