coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-03-21	{northbridge, soc, southbridge}/intel: Make use of generic set_subsystem()	Subrata Banik
2019-01-03	sb/intel/lynxpoint/pcie.c: Add more checks for NULL pointers	Tristan Corrick
2018-12-28	sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports	Tristan Corrick
2018-12-07	sb/intel/lynxpoint/pcie.c: Fix a mistake in a comment	Tristan Corrick
2018-06-09	sb/intel/lynxpoint: Get rid of device_t	Elyes HAOUAS
2018-04-20	pci: Move inline PCI functions to pci_ops.h	Patrick Rudolph
2017-07-10	southbridge/intel/lynxpoint: Fix undefined behavior	Ryan Salsamendi
2017-07-02	southbridge/intel/lynxpoint: Fix undefined behavior	Ryan Salsamendi
2016-12-06	PCI ops: Define read-modify-write routines globally	Kyösti Mälkki
2016-02-23	southbridge/intel/lynxpoint: Use common gpio.c	Patrick Rudolph
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2013-12-21	haswell: Misc updates from 1.6.1 ref code	Duncan Laurie
2013-12-21	lynxpoint: Add devicetree config option to force enable ASPM	Duncan Laurie
2013-12-05	lynxpoint: enable clock gating	Aaron Durbin
2013-12-05	lynxpoint: implement additional programming steps	Stefan Reinauer
2013-12-05	lynxpoint: disable pcie devices based on config	Aaron Durbin
2013-12-02	lynxpoint: move all pcie device handling to pcie.c	Aaron Durbin
2013-08-01	intel/lynxpoint: remove explicit pcie config accesses	Kyösti Mälkki
2013-03-14	lynxpoint: Update device IDs and clock gating setup	Duncan Laurie
2013-03-14	haswell: Add initial support for Haswell platforms	Aaron Durbin