coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2013-04-01	lynxpoint: Rework ACPI NVS to add new SerialIO variables	Duncan Laurie
	This reclaims space in ACPI NVS by removing unused fields and adds new fields for SerialIO BARs which will be used to communicate the allocated resources to ACPI. Change-Id: I002bf396cf7b495bc5b7e54b741527e507aff716 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2969 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-14	haswell: Add initial support for Haswell platforms	Aaron Durbin
	The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore, the southbridge support is included as well. The basis for this code is the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires more attention, but this is a good starting point. This code partially gets up through the romstage just before training memory on a Haswell reference board. Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2616 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>