coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-01-04	sb/intel: Use `bool` for PCIe coalescing option	Angel Pons
2020-11-10	sb/intel/lynxpoint/sata: Always use AHCI mode	Angel Pons
2020-10-14	haswell/lynxpoint: Align cosmetics with Broadwell	Angel Pons
2020-09-21	src/southbridge: Drop unneeded empty lines	Elyes HAOUAS
2020-07-28	lynxpoint: Factor out PIRQ routing from devicetree	Angel Pons
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-04	src/southbridge: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2019-08-21	southbridge/intel: Tidy up preprocessor and headers	Kyösti Mälkki
2018-11-16	sb/intel/lynxpoint: Generate the ACPI FADT with a common function	Tristan Corrick
2018-11-01	src: Add missing include <stdint.h>	Elyes HAOUAS
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-07-11	intel/lynxpoint: Allow to always route USB3 ports to XHCI	Stefan Reinauer
2014-07-04	intel/lynxpoint: Add SATA DEVSLP disable option	Marc Jones
2013-12-21	lynxpoint: Add configuration option for SATA gen3 DTLE registers	Shawn Nematbakhsh
2013-12-21	lynxpoint: Add devicetree config option to force enable ASPM	Duncan Laurie
2013-12-21	lynxpoint: me: Support ICC clock enables message	Duncan Laurie
2013-04-01	lynxpoint: Basic configuration of SerialIO devices	Duncan Laurie
2013-03-21	haswell/lynxpoint: Use new PCH/PM helper functions	Duncan Laurie
2013-03-14	lynxpoint: Update device IDs and clock gating setup	Duncan Laurie
2013-03-14	haswell: Add initial support for Haswell platforms	Aaron Durbin