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2024-04-17sb/intel/ibexpeak: Drop USB3 settings from devicetreeKeith Hui
ibexpeak has no USB 3 capabilities. They were kept briefly when its devicetree structure was split from bd82x6x in commit ab4de83f4330 ("sb/intel/ibexpeak: Sever bd82x6x source dependency") to verify correctness. With that done, they can go. Change-Id: I6b847e1532d2e84a7b408a8858c8613b322d0373 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-04-16sb/intel/ibexpeak: Sever bd82x6x source dependencyKeith Hui
It shares southbridge devicetree definition with bd82x6x, causing changes made there to break builds for boards with this PCH. Give ibexpeak its own copy. TEST=abuild tested with lenovo/t410, lenovo/x201, packardbell/ms2290. Timeless binary did not change for all. Change-Id: I08229ca658bd9c360b6be6137d882d319041b730 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81889 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12tree: Drop duplicated <device/{path,resource}.h>Elyes Haouas
<device/device.h> is supposed to provide <device/{path,resource}.h> Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-23arch/x86/ioapic: use uintptr_t for IOAPIC base addressFelix Held
Use uintptr_t for the IOAPIC base parameter of the various IOAPIC- related functions to avoid needing type casts in the callers. This also allows dropping the VIO_APIC_VADDR define and consistently use the IO_APIC_ADDR define instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I912943e923ff092708e90138caa5e1daf269a69f Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-24southbridge: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic80d27a963da8eddc3d1f0d9a3d59763028d4ed0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80075 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-11-10device/Kconfig: rename AZALIA_PLUGIN_SUPPORT to AZALIA_HDA_CODEC_SUPPORTFelix Held
Rename AZALIA_PLUGIN_SUPPORT to AZALIA_HDA_CODEC_SUPPORT and add a help text to this Kconfig option to clarify what this option is about. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71e36869c6ebf77f43ca78f5e451aebfb59f1c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-08-08ACPI: Add helper fill_fadt_extended_pm_io()Kyösti Mälkki
Once platform code has filled in the (legacy) ACPI PM register map, added function will fill in the extended entries in FADT. TEST=samsung/lumpy and amd/mandolin FADT stays unchanged. Change-Id: I90925fce35458cf5480bfefc7cdddebd41b42058 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-05sb/intel/ibexpeak/Kconfig: Remove SOUTH_BRIDGE_OPTIONSElyes Haouas
Remove dummy SOUTH_BRIDGE_OPTIONS. Change-Id: Ifce7965040d96486ee8de2fba2ead9c54ee9a9f9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76948 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-14sb/intel/bd82x6x,ibexpeak: Move UPRWC definitionKyösti Mälkki
Locate it with all the other PM IO registers. Change-Id: I779b2e313c9d8370c66c4adb4f6f4d4cf5b4e7dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-04-29sb,soc/amd,intel: Drop include <cpu/x86/smm.h>Kyösti Mälkki
I forgot to remove these in commit 0fe36db154eb ("ACPI: Make FADT entries for SMI architectural"). Change-Id: Ib1bc1dad6053ddb0454d4510917fd2bcf0901f35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74811 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-29ACPI: Make FADT entries for RTC/CMOS architecturalKyösti Mälkki
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY that points to same offset. Since the century field inside RTC falls within the NVRAM space, and could interfere with OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY. There were no reference for the use of offset 0x48 for century. Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-27ACPI: Make FADT entries for SMI architecturalKyösti Mälkki
Change-Id: I80aa71b813ab8e50801a66556d45ff66804ad349 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74600 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-26sb/intel: Use ACPI_COMMON_MADT_IOAPICKyösti Mälkki
i82801gx, i82801ix, i82801jx: Maintain IRQ #0 to GSI #2 override as positive edge trigger. ibexpeak, emulation/qemu-q35: Change IRQ #0 to GSI #2 override to positive edge trigger from the bus ISA default (positive edge). Change-Id: Ia8a04daf3a79d9f2f4801dc85e4975278e30dc8a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26arch/x86/ioapic: Promote ioapic_get_sci_pin()Kyösti Mälkki
Platform needs to implement this to provide information about SCI IRQ pin and polarity, to be used for filling in ACPI FADT and MADT entries. Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-21ACPI: Obsolete FADT duty_offset and duty_width fieldsKyösti Mälkki
After the obsoletion of Processor() it is necessary to provide _PTC package to define P_CNT IO address for clock throttling. The platforms touched here already emit empty _PTC to disable clock throttling. Change-Id: I0e84c8ccd2772c9b3d61f71b74324c8d28f4eefe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74438 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fieldsKyösti Mälkki
After the obsoletion of Processor() it is necessary to provide _CST package to define P_LVLx IO addresses for C2/C3 transitions. The latency values from _CST will always replace those in FADT. Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-17sb/intel: Use ACPI_FADT_C2/C3_NOT_SUPPORTED definesKyösti Mälkki
Change-Id: I242e05ee63f46bedbab3a425e922e60f1c749a15 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-15sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPICKyösti Mälkki
Boards with SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID have special handling for the time being. Change of aopen/dxplplusu is coupled with sb/intel/i82801dx. Change of emulation/qemu-i440fx is coupled with intel/i82371eb. For asus/p2b, this adds MADT LAPIC entries, even though platform has ACPI_NO_MADT selected. Even previously ACPI_NO_MADT creates the MADT, including an entry for LAPIC address. Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-01treewide: Remove duplicated include <device/pci.h>Elyes Haouas
<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12treewide: Remove unused <cpu/x86/smm.h>Elyes Haouas
Change-Id: Iba5b39c6189d3224ba209c7985153701fe8896fb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-23mb,x86/smm: Disable unused IO trapsKyösti Mälkki
Only IO trap #3 for lenovo/x60,t60 and getac/p470 have implemented the IO trap handler. Change-Id: Ibadce174f673e88380f4b6745fd9ed8b73177a13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70367 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09sb/intel/ibexpeak/Makefile.inc: Remove path to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: I7c2217bbe677810d25c5d5d1062320773ee7e0c8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70386 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-07sb,soc/intel: Fix SMI handler IO trap data maskKyösti Mälkki
Shift is done in multiples of 8 (1 << 3) bits. It was fixed already for i82801ix/jx. Change-Id: I5e1c2b3bf4ba68f34eb43e59fe783d5cd6e0a39a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-28sb,soc/intel: Apply transitional flag TCO_SPACE_NOT_YET_SPLITKyösti Mälkki
Tree is inconsistent with the use of TCO register space offsets and related preprocessor defines. The legacy space was offset from ACPI PM base by 0x60, but this changed with later platforms. The convenient way is to define the TCO registers relative to its base address and subtract 0x60 here, but this change cannot be easily done tree-wide or in one go. For the transient period, apply TCO_SPACE_NOT_YET_SPLIT flag until all platforms use a clean style of tco_{read,write} accessor functions instead of {read,write}_pmbase16(), or worse, inw/outl(). Change-Id: I16213cdb13f98fccb261004b31e81a9a44cb6e3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-25ACPI: Use common code for MADT LAPIC NMIsKyösti Mälkki
Use the broadcast ID to deliver LINT1 as NMI to all CPUs, instead of listing individual LAPIC IDs. Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-22src/southbridge: Remove unnecessary space after castsElyes Haouas
Change-Id: Ib82968724696110a8d1655928db5b2a665525d20 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69805 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17sb/intel/common: Fix GPE0 related register conflictKyösti Mälkki
When ACPI GPE0 block was extended to 64 events or 8 bytes, ACPI PM register space was slightly modified. After adjustment, PM2_CNT register moved to 0x50 where register SS_CNT was previously defined to be. For platforms that have a valid use for PM2_CNT==0x50 in their FADT, remove overlapping definition of SS_CNT. On i82801dx/gx ACPI GPE0 supports 32 events, reset_gpe0_status() incorrectly addressed also GPE0_EN register. For a bit cleaner implementation, define GPE0_HAS_64_EVENTS. Change-Id: Iec83e9010146ebd487a61f542ac5c6f4c6a60833 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-10sb,soc/intel: Use register_new_ioapic_gsi0()Kyösti Mälkki
Change-Id: I6b0e4021595fb160ae3bf798468f4505b460266f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10sb,soc/intel: Use acpi_create_madt_ioapic_from_hw()Kyösti Mälkki
Change-Id: I9fd9cf230ce21674d1c24b40f310e5558e65be25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-03treewide: Add 'IWYU pragma: export' commentElyes Haouas
This pragma says to IWYU (Include What You Use) that the current file is supposed to provide commented headers. Change-Id: I482c645f6b5f955e532ad94def1b2f74f15ca908 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-10-15treewide: Use 'fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk'Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaecb83c3bc9c75dab427a3ca54da1e6a8f87cf9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-15treewide: Use 'fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk'Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id3002dc976b82f71b1f60a6e32b16d60a7bbbead Reviewed-on: https://review.coreboot.org/c/coreboot/+/68427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-12treewide: Use 'fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ic48c5c165732c8397c06a2362191a94ae5805cf1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7ddb4ea792b9a2153b7c77d2978d9e1c4544535d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'pm2_cnt_len' for 'x_pm2_cnt_blk.bit_width'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I040ddab8845cc2191c6ca5af7f132ec8a504bccf Reviewed-on: https://review.coreboot.org/c/coreboot/+/68274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'gpe0_blk' for 'x_gpe0_blk.addrl'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I05d5097097b925a7bc8058f4c23e7c13a49f03c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'gpe0_blk_len' for 'x_gpe0_blk.bit_width'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I581cacb6086d94fe65e6f4800454f447e1ada07b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm_tmr_len' for 'x_pm_tmr_blk.bit_width'Elyes Haouas
Change-Id: Id4e2939b74ec93f50a4bedd0069090f0775b0556 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm1_cnt_len' for 'x_pm1a_cnt_blk.bit_width'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I4e468e6bb58adc44bd66149eb79dc885dbf73c67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm1_evt_len' for 'x_pm1a_evt_blk.bit_width'Elyes Haouas
Change-Id: I1e51ccad32f1c5e692c76b331eedf4d3bb260d38 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-06treewide: use predicates to check for enabled pci devicesFabio Aiuto
use functions to check for pci devices instead of open-coded solution. TEST: compiled and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: Idb992904112db611119b2d33c8b1dd912b2c8539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68102 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-23{sb,soc}/intel: Do not require hda_verb.cAngel Pons
Just use the conditional inclusion through `device/Makefile.inc`. Change-Id: Id363a97460ae2cfe4b10d491d4ef06394eb530c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-07-14sb/intel/ibexpeak: Perform const correctnessBill XIE
me_bios_path_values[] in me.c should not be mutable. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I56412ff0883e1d37027b989c7ac1bd83e93661f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-14commonlib: Substitude macro "__unused" in compiler.hBill XIE
Since there are many identifiers whose name contain "__unused" in headers of musl libc, introducing a macro which expands "__unused" to the source of a util may have disastrous effect during its compiling under a musl-based platform. However, it is hard to detect musl at build time as musl is notorious for having explicitly been refusing to add a macro like "__MUSL__" to announce its own presence. Using __always_unused and __maybe_unused for everything may be a good idea. This is how it works in the Linux kernel, so that would at least make us match some other standard rather than doing our own thing (especially since the other compiler.h shorthand macros are also inspired by Linux). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-25sb/intel/ibexpeak/early_pch.c: Use PCI_BASE_ADDRESS_0 macroElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: If74e1db623d65d639041d49caf0ca1b6c0e1f2ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/62326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25nb/intel/ironlake: Fix sending HECI messagesArthur Heymans
This code only worked when the payload (a packed struct) was 4 byte aligned. With gcc11 this happens to not be the case. Change-Id: I5bb4ca4b27f8554208b12da177c51091ea6a108f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25arch/x86/Kconfig: add HPET_MIN_TICKSFelix Held
Some Intel southbridges have HPET_MIN_TICKS in their Kconfig files, but the CONFIG_HPET_MIN_TICKS symbol is used in the common acpi code in acpi/acpi.c, so define this option in arch/x86/Kconfig to have it defined in all cases where the function that ends up using this information gets called. Since we now have the type information for this Kconfig option in a central place, it can be dropped from the Kconfig file of the Intel southbridges that change the default value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibe012069dd4b51c15a8fbc6459186ad2ea405a03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62298 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24nb/intel/ironlake: Move out HECI remainders into southbridgeAngel Pons
Move the remaining HECI-related stuff to southbridge scope, as the HECI hardware is in the southbridge. Note that HECI BAR is now enabled a bit earlier than before, but this shouldn't matter. Change-Id: I4a29d0b5d5c5e22508bcdfe34a1c5459ae967c75 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-22sb/intel/ibexpeak: Constify struct southbridge_intel_ibexpeak_configElyes Haouas
Change-Id: I096ccd0ec224b98038d290422f568666bbede43a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22treewide: Get rid of CONFIG_AZALIA_MAX_CODECSElyes Haouas
Get rid of Kconfig symbol introduced at commit 5d31dfa8 High Definition Audio Specification Revision 1.0a says, there are 15 SDIWAKE bits. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ib8b656daca52e21cb0c7120b208a2acdd88625e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62202 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15nb/intel/ironlake/raminit_heci.c: Move to southbridge scopeAngel Pons
HECI stuff is in the southbridge, so put the code in there. Rename the file to match the name of the function it provides. Change-Id: I71de1234547dbd46a9b4959c619d2ae194da620a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-12sb/intel/ibexpeak/azalia.c: Use 'pci_{and,or}_config'Elyes HAOUAS
Change-Id: Iafe1a3476c0afa5ebfb75fb704429594e24e96f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11device/azalia_device: Drop unused function parameterAngel Pons
The `dev` parameter of the `azalia_codecs_init()` function is not used. Remove it, and update all call sites accordingly. Change-Id: Idbe4a6ee5e81d5a7fd451fb83e0fe91bd0c09f0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59119 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11sb/intel/ibexpeak: Use `azalia_codecs_init()`Angel Pons
Use the functionally-equivalent common Azalia code to get rid of redundant code. Change-Id: Ib3b40e5788c6315cad02b670346997c9179e5fab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-11sb/intel: Use `azalia_program_verb_table()` functionAngel Pons
Use the `azalia_program_verb_table()` function in preparation to deduplicate Azalia init code. With this change, the "Azalia: verb loaded." message is now printed when programming the verbs failed. This will be addressed once `codec_init()` has been deduplicated. Change-Id: I5d9e0f19429620166f2a6ef48ec7c963ee64b59c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-04sb/intel: Replace bad uses of `find_resource`Angel Pons
The `find_resource` function will never return null (will die instead). In cases where the existing code already accounts for null pointers, it is better to use `probe_resource` instead, which returns a null pointer instead of dying. Change-Id: I13c7ebeba2e5a896d46231b5e176e5470da97343 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-22arch/x86/ioapic: Select IOAPIC with SMPKyösti Mälkki
For coreboot proper, I/O APIC programming is not really required, except for the APIC ID field. We generally do not guard the related set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC). In practice it's something one cannot leave unselected, but maintain the Kconfig for the time being. Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22sb,soc/intel: Replace set_ioapic_id() with setup_ioapic()Kyösti Mälkki
This adds delivery of PIC/i8259 interrupts via ExtNMI on the affected platfoms. Change-Id: If99e321fd9b153101d71e1b995b43dba48d8763f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-22sb,soc/intel: Set IOAPIC max entries before APIC IDKyösti Mälkki
This allows to replace set_ioapic_id() call with setup_ioapic() that also clears redirection table entries. Change-Id: I854f19c997a96bcdccb11a0906431e3291788cb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-22sb,soc/intel: Set IOAPIC redirection entry countKyösti Mälkki
The number of redirection table entries (aka interrupt vectors) inside an I/O APIC may depend of the SKU, with the related register being of type read/write-once. Provide support utilities to either lock or set this registers value. Change-Id: I8da869ba390dd821b43032e4ccbc9291c39e6bab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-05src/soc to src/superio: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-17sb/intel/ibexpeak/early_cir: add missing arch/cpu.h includeFelix Held
Including arch/cpu.h is needed to have the declaration for cpuid_eax, get_fms and struct cpuinfo_x86. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I18b60f8cf33f71c7215a97ea209b8f8cf66cf42f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17sb/intel/bd82x6x,ibexpeak,lynxpoint/me.h: add missing includesFelix Held
Include device/device.h to have struct device defined and types.h to have bool, u8, u16 and u32 defined. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3c5d5a78c2e2dab21432ced5f84665eb78a49d52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-08-19acpi: Fill fadt->century based on KconfigNico Huber
Change-Id: I916f19e022633b316fbc0c6bf38bbd58228412be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16arch/x86/ioapic: Drop irq_on_fsb as a configurable itemKyösti Mälkki
APIC Serial Bus pins were removed with ICH5 already, so a choice 'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG 0x3 is also not documented since ICH5. For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was wrong and ignored as BOOT_CONFIG register emulation was never implemented. For ICH4 and earlier, the choice to use FSB can be made based on the installed CPU model but this is now just hardwired to match P4 CPUs of aopen/dxplplusu. For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined and the only possible operation mode there is APIC Serial Bus, which requires no configuration. Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07sb/intel/ibexpeak: Drop P_LVLx support in FADTAngel Pons
IO MWAIT redirection is not enabled. The code is missing, but C-states should instead be reported using the _CST ACPI object. Change-Id: I21fd2fa6ee4aa1ed57694549d5cb48159f37af26 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-16sb/intel: Drop outdated SMBus I/O BAR commentAngel Pons
The SMBus I/O bar is not relocated because it's reported to the allocator as a fixed resource. Drop these out-of-date comments. Change-Id: I0149764fd231b3a4e56a5a9b7f4ae61f7954cf7a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-06src: Retype option API to use unsigned integersAngel Pons
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-04-27sb/intel/common: Refactor _PRT generation to support GSI-based tablesTim Wawrzynczak
Newer Intel SoCs also support _PRT tables, but they route PCI devices to more than just PIRQs, and statically specify IRQs instead of using link devices. Extend/refactor intel_acpi_gen_def_acpi_pirq to support this additional use case. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-21{sb,soc}/intel: Use `get_int_option` functionAngel Pons
Change-Id: I05f724785880089a513319d70dfd70fc2a6b7679 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-21sb/intel/x/sata.c: Use `get_int_option` for `sata_mode`Angel Pons
Change-Id: Ifd1f3969281e67d1a6ab7eb99dd048799c0cb17d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-11sb/intel/x/smbus.c: Correct register access widthAngel Pons
The register is 16 bits wide. Change-Id: I58d44a17613965e0a27aab5246dcdce68e1a8201 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-27sb/intel/ibexpeak: Drop useless bd82x6x pcie.cAngel Pons
The PCIe device IDs for Ibexpeak are not in bd82x6x's pcie.c driver. Thus, the code has always been dead code on Ibexpeak. Drop it. Change-Id: Ide2b4af2a187ecf98f39a9c979646a7ed959c74f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51067 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27sb/intel/ibexpeak: Add all PCI IDs for LPCAngel Pons
Taken from document 322170-028 (5 series specification update). Tested on out-of-tree HP ProBook 6550b (HM57), fixes several issues. Without this patch, EHCI controllers had no IRQ assigned and there were unexpected exceptions about NMIs. With this patch, the issues are gone. Change-Id: Icd31dd89ba49e38a5e4c108a8361dbf636332ab8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51066 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18sb/intel/ibexpeak: Drop obsolete SATA register settingsAngel Pons
Code was copy-pasted from older chips and has no effect on ibexpeak. Change-Id: I3c5b2b8e4aa6211975c3e3dc1d64432886ef9352 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47864 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16sb/intel/*/lpc: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: I8f8655853fd1fc1f3679a4549fdaa08702f96c7b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-12sb/intel/x/lpc.c: Drop commented-out `gpio_init` callAngel Pons
Change-Id: I4255c63f87e8243237204ac86eb85e34b5aaa225 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-12sb/intel/x/lpc.c: Drop `pch_disable_smm_only_flashing`Angel Pons
The southbridge common SPI support already does this. Tested on Asrock B85M Pro4, internal flashing and MRC cache still work. Change-Id: I7ce0ca584cd3d42a10cdb74f45742f1eadc01bfa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-11sb/intel/ibexpeak: Drop Global NVS supportAngel Pons
Was copy-pasted from bd82x6x and no mainboard actually needs it. The few globals moved outside the GNVS will be removed, relocated or replaced with acpigen later. Change-Id: I590a355f1bd1e54365b2e329cfdc62384446a15c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49280 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11ACPI: Move PICM declarationKyösti Mälkki
Variable PICM was not inside GNVS region and can use a static initialisation value. For most AMD platforms PICM default changes from 1 to 0. Fix comments about PICM==0 used to indicate use of i8259 PIC for interrupt delivery. Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11sb,soc/intel: Drop OSYS from GNVSKyösti Mälkki
The value should be set by OSPM using some combination of _OSI() queris in the \_SB._INI() method. To maintain previous behaviour with this commit, boards where GNVS osys initialisation was removed now do the same in ASL. Change-Id: Id4957b12a72fbf7fa988e7ff039e47abcc072e1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49353 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11mainboards: Drop PWRS from GNVSKyösti Mälkki
Initialize variable to 1 to indicate AC power supply. If platform has EC it will set this correctly based on whether plugged on the charger or not. Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
Drop unused sandybridge.h includes to avoid build failures on Ironlake. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: If2f0147fe50266e2fe2098cafdf004e51282f5e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-07sb/intel: Extract `set_global_reset` functionAngel Pons
To avoid duplicating this function in ramstage, factor it out. Change-Id: I64c59a01ca153770481c28ae404a5dfe8c5382d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-06sb/intel/{bd82x6x,ibexpeak}: hide MEI if ME inoperableJames Ye
- Add Kconfig option to hide the Management Engine Interface device so the OS doesn't try to access it, if the Management Engine is in an inoperable mode, e.g. if me_cleaner is used. - Also hide the MEI if the ME is in Soft Temp Disable mode. Change-Id: Ie4a35bf5fc196e0a02b7591cdb8633d38f0c7f3e Signed-off-by: James Ye <jye836@gmail.com> Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39074 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06sb,soc/intel: Add wake source fields in GNVSKyösti Mälkki
For the moment, these are most not used but become a necessity for a unified <soc/nvs.h> approach. They would be required for the implementation of _SWS method for OSPM to determine the reason for system waking up. The related hardware registers are present with these platforms. It's expected that ACPI power-management related GNVS entries are grouped together to form a single struct in later works. Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50193 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05intel: Turn `DEFAULT_RCBA` into a Kconfig symbolAngel Pons
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases where a pointer cast would be necessary. Instances in Sandy Bridge MRC code were left as-is intentionally, so as not to collide with another cleanup patch train. Tested with BUILD_TIMELESS=1, these boards remain identical: - Asus P8Z77-V LX2 - Packard Bell MS2290 Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-02treewide [Kconfig]: Remove useless commentElyes HAOUAS
Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-30sb/intel/ibexpeak: Drop invalid ME finalisation functionAngel Pons
Was copied from bd82x6x and none of the PCI IDs matches that of Ibex Peak (PCI_DID_INTEL_IBEXPEAK_HECI1 = 0x3b64). Remove the code. This allows dropping the me_8.x.c dependency, which never made sense. Change-Id: I54df1e080048c0599dbee687ec617fb724cb6634 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-29soc/intel: Drop CMEM from GNVSKyösti Mälkki
Already tagged as obsolete_cmem in <soc/nvs.h> files. Change-Id: I8ba2a79f866fa07f1b4ae7291c72c91db5027911 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50043 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28ACPI: Declare GNVS variables globallyKyösti Mälkki
There is a common place where acpigen generates these, so the declarations for the OperationRegions should be centralized too. Change-Id: I772492ca9e651b60244c565d1e926dc2ad33cfd8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49795 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-20ACPI GNVS: Drop APIC, factor out MPENKyösti Mälkki
APIC was not referenced anywhere in ASL. MPEN has references under boards: getac/p470, roda/rk9, roda/rk886ex. MPEN has reference also in Intel SpeedStep ASL. Replace static MPEN with detection of multiple CPUs installed. Change-Id: Ib5f06416b23196b7227ccd5814162925c31c084b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-20ACPI GNVS: Drop most dev_count_cpu()Kyösti Mälkki
Only amd/picasso and amd/stoneyridge have reference to PCNT and that could be replaced with acpigen. Remove the PCNT name from GNVS OperationRegion elsewhere. Change-Id: I7dd45a840b3585fd24c31fd923b991c34ab4d783 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-18ACPI: Refactor ChromeOS specific ACPI GNVSKyösti Mälkki
The layout of GNVS has expectation for a fixed size array for chromeos_acpi_t. This allows us to reduce the exposure of <chromeos/gnvs.h>. If chromeos_acpi_t was the last entry in struct global_nvs padding at the end is also removed. If device_nvs_t exists, place a properly sized reserve for chromeos_acpi_t in the middle. Allocation from cbmem is adjusted such that it matches exactly the OperationRegion size defined inside the ASL. Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-18ACPI: Select ACPI_SOC_NVS only where suitableKyösti Mälkki
Having some symmetry with <soc/nvs.h> now allows to reduce the amount of gluelogic to determine the size and cbmc field of struct global_nvs. Since GNVS creation is now controlled by ACPI_SOC_NVS, drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne cannot have this selected until <soc/nvs.h> exists. Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao
2021-01-13sb/intel: Add CBMC entries in GNVSKyösti Mälkki
While unused, this allows use of a common initialisation code for GNVS allocation. Change-Id: Ie84b5a3e16d3baa12bcd5dadac0b1f7edb323272 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-13ACPI: Have single call-site for acpi_inject_nvsa()Kyösti Mälkki
Change-Id: I61a9b07ec3fdaeef0622df82e106405f01e89a9e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48719 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-13ACPI: Add common acpi_fill_gnvs()Kyösti Mälkki
Change-Id: I515e830808a95eee3ce72b16fd26da6ec79dac85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48718 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 15:04:18 +0000