coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-06-12	sb/intel/i82801jx: Use PCI bitwise ops	Angel Pons
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-01	sb/intel/i82801jx: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-04-04	src/southbridge: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2019-12-19	src/southbridge: Remove unused <stdlib.h>	Elyes HAOUAS
2019-08-21	southbridge/intel: Tidy up preprocessor and headers	Kyösti Mälkki
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2019-01-06	device: Use pcidev_path_on_root()	Kyösti Mälkki
2019-01-06	device: Use pcidev_on_root()	Kyösti Mälkki
2018-08-16	sb/intel/i82801[ij]x: do not set Chipset Initialization Register (CIR) 5	Stefan Tauner
2018-08-14	sb/intel/i82801[ij]x: use (more) RCBA register names instead of magic numbers	Stefan Tauner
2018-05-24	sb/intel/i82801jx: Get rid of device_t	Elyes HAOUAS
2017-07-21	I82801JX: Add IS_ENABLED around config options	Martin Roth
2017-07-21	sb/intel/i82801jx: Add correct PCI ids and change names	Arthur Heymans