coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-06-12	sb/intel/i82801ix: Use PCI bitwise ops	Angel Pons
2020-06-06	src: Use pci_dev_ops_pci where applicable	Angel Pons
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-01	sb/intel/i82801ix: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-04-04	src/southbridge: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2019-11-22	sb/i82801ix: Use macros instead of hard-coded IDs	Felix Singer
2019-10-01	intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL	Kyösti Mälkki
2019-03-21	{northbridge, soc, southbridge}/intel: Make use of generic set_subsystem()	Subrata Banik
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2018-05-24	sb/intel/i82801ix: Get rid of device_t	Elyes HAOUAS
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-06-04	devicetree: Change scan_bus() prototype in device ops	Kyösti Mälkki
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-11-19	i82801ix,bd82x6x,ibexpeak: rewrite expresscard hotplug	Vladimir Serbinenko
2014-07-08	southbridge: Trivial - drop trailing blank lines at EOF	Edward O'Callaghan
2013-09-10	intel/i82801ix: remove explicit pcie config accesses	Kyösti Mälkki
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-11-27	intel/i82801ix: new southbridge, ICH9	Patrick Georgi