coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-12-02	sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}	Elyes Haouas
2022-01-04	sb/intel: Use `bool` for PCIe coalescing option	Angel Pons
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-04	src/southbridge: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2019-11-12	sb/intel/i82801gx: Add common LPC decode code	Arthur Heymans
2019-07-20	mb/,sb/intel/i82801gx: Merge `ide_legacy_combined` into `sata_mode`	Nico Huber
2019-06-06	sb/intel/i82801gx: Detect if the southbridge supports AHCI	Arthur Heymans
2019-01-17	sb/intel/i82801gx: Implement PCIe coalescing	Arthur Heymans
2018-11-01	src: Add missing include <stdint.h>	Elyes HAOUAS
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-11-04	i82801gx: Handle whole FADT in southbridge.	Vladimir Serbinenko
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-08-22	Auto-declare chip_operations	Kyösti Mälkki
2011-10-27	i82801gx: Fix port status in AHCI mode	Sven Schnelle
2011-10-25	i82801gx: Add setting for C4onC3 mode	Sven Schnelle
2010-02-15	Various license header consistency fixes (trivial).	Uwe Hermann
2009-10-26	Kontron 986LCD-M update	Stefan Reinauer
2009-03-11	This patch contains some significant updates to the i82801gx component and will	Stefan Reinauer
2009-01-20	Update Kontron board	Stefan Reinauer
2008-10-29	Support for the Intel ICH7 southbridge.	Stefan Reinauer