coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2008-04-01	The early init code of several Intel southbridge chipsets calls	Ed Swierk
2007-11-04	Restructure the PCI IDs list for the ICH* chipsets from ICH/ICH0 up to	Uwe Hermann
2007-10-24	Ever wondered where those "setting incorrect section attributes for	Stefan Reinauer
2006-04-06	interesting behavior, i thought svn could do moves.	Stefan Reinauer
2006-04-06	break the tree really quick due to svn restrictions, next commit fill fix it	Stefan Reinauer
2005-09-21	Bug fixes: read all 16 bits of DMA configuration; set up NMI/SERR handling in...	Steven J. Magnani
2005-09-21	Bug fix: enable secondary IDE only if enable_b is set.	Steven J. Magnani
2005-09-21	Rewrite i82801er_enable to do nothing if device does not have an enable/disab...	Steven J. Magnani
2005-07-08	eric patch	Yinghai Lu
2005-07-06	Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51	arch import user (historical)
2004-11-04	- Update abuild.sh so it will rebuild successfull builds	Eric Biederman
2004-11-02	* empty log message *	Yinghai Lu
2004-10-22	* empty log message *	Yinghai Lu
2004-10-22	- kill typo so resources are not mixed up in amdk8/northbridge.c	Eric Biederman
2004-10-21	- Bump the LinuxBIOS major version	Eric Biederman
2004-10-16	- Make all ports use config.h for if they have chip_config or chip_info struc...	Eric Biederman
2004-10-16	- First stab at running linuxbios without the old static device tree.	Eric Biederman
2004-07-01	Intel E7501 P64H2 ICH5R support	Yinghai Lu