coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2008-04-01	The early init code of several Intel southbridge chipsets calls	Ed Swierk
2007-11-04	Restructure the PCI IDs list for the ICH* chipsets from ICH/ICH0 up to	Uwe Hermann
2007-10-24	Ever wondered where those "setting incorrect section attributes for	Stefan Reinauer
2006-12-14	In the file mainboard/intel/i82801dbm/i82801dbm.c the variable	Jon Dufresne
2006-11-05	Use the canonical name of the vendors/devices and the	Uwe Hermann
2005-09-21	Bug fixes: read all 16 bits of DMA configuration; set up NMI/SERR handling in...	Steven J. Magnani
2005-09-21	Bug fix: enable secondary IDE only if enable_b is set.	Steven J. Magnani
2005-09-21	Rewrite i82801dbm_enable to do nothing if device does not have an enable/disa...	Steven J. Magnani
2004-11-28	fixes to make adl855pc compile.	Ronald G. Minnich
2004-11-11	in loglevel.h, if ASM_CONSOLE_LOGLEVEL is defined, don't try to set it.	Ronald G. Minnich
2004-11-04	- Update abuild.sh so it will rebuild successfull builds	Eric Biederman
2004-10-22	- kill typo so resources are not mixed up in amdk8/northbridge.c	Eric Biederman
2004-10-21	- Bump the LinuxBIOS major version	Eric Biederman
2004-10-16	- Make all ports use config.h for if they have chip_config or chip_info struc...	Eric Biederman
2004-10-16	- First stab at running linuxbios without the old static device tree.	Eric Biederman
2004-09-30	digital logic stuff, fixes for the smbus code in 82801dbm	Ronald G. Minnich
2004-08-25	changes for the dbm part. Still need to remove the sata file ...	Ronald G. Minnich
2004-08-24	compiles.	Ronald G. Minnich
2004-08-24	new intel io hub.	Ronald G. Minnich