index
:
coreboot.git
macbookair5_2
macbookpro10_1
main
master
mbp101_medisable
mbp101_medisable_1
mbp82
x230
my copy of coreboot
User &
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
southbridge
/
intel
/
i3100
Age
Commit message (
Expand
)
Author
2010-04-27
Since some people disapprove of white space cleanups mixed in regular commits
Stefan Reinauer
2010-03-31
Drop \r\n and \n\r as both print_XXX and printk now do this internally.
Stefan Reinauer
2010-03-22
Fix all the format string warnings.
Myles Watson
2010-03-22
drop some unused files and fix warnings on i945 based systems.
Stefan Reinauer
2010-03-22
printk_foo -> printk(BIOS_FOO, ...)
Stefan Reinauer
2010-03-16
pci drivers should be const.
Stefan Reinauer
2010-02-22
This is a general cleanup patch
Stefan Reinauer
2010-02-15
Various license header consistency fixes (trivial).
Uwe Hermann
2010-02-07
newconfig is no more.
Patrick Georgi
2010-01-18
Move all IOAPIC selection to southbridges, and remove them
Patrick Georgi
2010-01-16
coreboot has 13 instances of IOAPIC setup distributed across a lot
Stefan Reinauer
2009-10-09
Remove default n statements to simplify .config and ldoptions files.
Myles Watson
2009-09-25
some progress on kconfig:
Patrick Georgi
2009-08-28
This patch adds VGA and PS/2 Keyboard/mouse support to the already existing i...
Arnaud Maye
2009-07-02
Move the v3 resource allocator to v2.
Myles Watson
2009-07-01
Add support for the Intel Eagle Heights development board.
Thomas Jourdan
2009-06-03
Revert "CMOS: Add set_option and rework get_option."
Luc Verhaegen
2009-06-03
CMOS: Add set_option and rework get_option.
Luc Verhaegen
2009-02-28
coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3
Stefan Reinauer
2008-09-03
Tidy up identifiers, per Uwe's suggestion. Trivial.
Ed Swierk
2008-08-25
This patch adds PCI device IDs for the Intel EP80579 Integrated Processor,
Ed Swierk
2008-08-25
This patch modifies the Intel 3100 southbridge code to recognize the
Ed Swierk
2008-05-07
Implement GPIO configuration routines for the Intel 3100 southbridge,
Ed Swierk
2008-04-30
By default, the Intel 3100 LPC interface enables only I/O range 0x3f8
Ed Swierk
2008-04-01
Setting an integrated southbridge device (like SATA or USB2.0) to
Ed Swierk
2008-04-01
Tiny style fix for consistency (trivial).
Ed Swierk
2008-04-01
The early init code of several Intel southbridge chipsets calls
Ed Swierk
2008-03-30
Like other Intel chipsets, the Intel 3100 has a TCO timer that reboots
Ed Swierk
2008-03-16
Here is an updated patch addressing most of Uwe's and Peter's ...
Ed Swierk
