coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2009-06-03	CMOS: Add set_option and rework get_option.	Luc Verhaegen
2009-02-28	coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3	Stefan Reinauer
2008-09-03	Tidy up identifiers, per Uwe's suggestion. Trivial.	Ed Swierk
2008-08-25	This patch adds PCI device IDs for the Intel EP80579 Integrated Processor,	Ed Swierk
2008-08-25	This patch modifies the Intel 3100 southbridge code to recognize the	Ed Swierk
2008-05-07	Implement GPIO configuration routines for the Intel 3100 southbridge,	Ed Swierk
2008-04-30	By default, the Intel 3100 LPC interface enables only I/O range 0x3f8	Ed Swierk
2008-04-01	Setting an integrated southbridge device (like SATA or USB2.0) to	Ed Swierk
2008-04-01	Tiny style fix for consistency (trivial).	Ed Swierk
2008-04-01	The early init code of several Intel southbridge chipsets calls	Ed Swierk
2008-03-30	Like other Intel chipsets, the Intel 3100 has a TCO timer that reboots	Ed Swierk
2008-03-16	Here is an updated patch addressing most of Uwe's and Peter's ...	Ed Swierk