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path: root/src/southbridge/intel/fsp_rangeley/romstage.c
AgeCommit message (Expand)Author
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
2018-08-13src: Get rid of non-local header treated as localElyes HAOUAS
2017-01-12fsp 1.0 systems: Check for NULL when saving HobListPtrMartin Roth
2016-06-29intel romstage: Use run_ramstage()Kyösti Mälkki
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-14Revert "Remove FSP Rangeley SOC and mohonpeak board support"Martin Roth
2015-10-03Remove FSP Rangeley SOC and mohonpeak board supportAlexandru Gagniuc
2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-04-24fsp: Move fsp to fsp1_0Marc Jones
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
2015-02-09Intel FSP platforms: Fix timestampsKyösti Mälkki
2015-01-05timestamps: Switch from tsc_t to uint64_tStefan Reinauer
2014-12-16CBMEM console: Fix boards with BROKEN_CAR_MIGRATEKyösti Mälkki
2014-07-30southbridge/intel: Add fsp_rangeley supportMartin Roth
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