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2018-12-29sb/intel/bd828x6x: Make CONFIG_ELOG=y compileArthur Heymans
The function pch_log_state() was overlooked when making the smi relocation code common. Change-Id: I878772f1a93105b828e50f37e105d04988ba0bdf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-19southbridge: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Ia640131479d4221ccd84613033f28de3932b8bff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-12-18southbridge: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
Change-Id: Ic3f7d4d570cb5e343a9cf616e6e71935f9522b0a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-05sb/intel: Fix pointer castsPatrick Rudolph
Fix some compiler warnings due to pointer to integer conversions with different size. Required for 64bit ramstage. Change-Id: Ibfb3cacf25adfb4a242d38e4ea290fdc3929a684 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/29875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-05elog: make elog's SMM handler code follow everything elsePatrick Georgi
Instead of ELOG_GSMI_APM_CNT use APM_CNT_ELOG_GSMI and define it in cpu/x86/smm.h Change-Id: I3a3e2f823c91b475d1e15b8c20e9cf5f3fd9de83 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30022 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03sb/intel/common: Create a common PCH finalise implementationTristan Corrick
The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak. Lynx Point now benefits from being able to write-protect the flash chip. For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done in bd82x6x. Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is configured, flashrom reports all flash regions as read-only, and does not manage to alter the contents of the flash chip. Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to work as before. Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/29977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-28sb/intel/common: Fix style issue in spi.cElyes HAOUAS
Change-Id: I6b9e0e0c643f9b47cfe8bdfffbe247f477ace685 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-27sb/intel/i82801gx: Use common Intel SMM codeArthur Heymans
Use the common Intel code to set up smm and the smihandler. This is expected to break S3 resume and other smihandler related functionality as this code is meant to be used with CONFIG_SMM_TSEG. Platforms (i945, pineview, x4x) using this southbridge will adapt the CONFIG_SMM_TSEG codepath in subsequent patches. Tested on Intel D945GCLF, still boots fine but breaks S3 resume support because it hangs on SMI. Change-Id: If7016a3b98fc5f14c287ce800325084f9dc602a0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-26sb/intel/common: Fix style issue in spi.cPatrick Georgi
Change-Id: Ife8f7f164b26bea65a0dcde0cab339a1bb599e38 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/29834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan T <stefan.tauner@gmx.at> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-26sb/intel/spi: read FLCOMP descriptor early and cache itStefan Tauner
Change-Id: I4e5fe3ff083f2d0db1cfde16550b57537d5f7262 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/c/28349 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-22sb/intel/common: Reset Pre-OP after atomic SPI cycle is finishedWerner Zeh
Make sure that the Pre-Op register is cleared when an atomic cycle has been finished without errors. Change-Id: Ied88337125b125474b411e2f39f668171d15bfac Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-07sb/intel: Deduplicate vbnv_cmos_failed and rtc_initPatrick Rudolph
* Move all implementations to into common folder. * Add rtc.c for rtc based functions Allows all Intel based platforms to use VBOOT_VBNV_CMOS. Change-Id: Ia494e6d418af6f907c648376674776c54d95ba71 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-07intel: Get rid of smm_get_pmbasePatrick Rudolph
Change-Id: I2b3168c600a81502f9cd1ff3203c492cf026e532 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-01sb/intel/common: Create a common implementation of `acpi_fill_madt()`Tristan Corrick
The function `acpi_fill_madt()` is identical among all the Lynx Point boards and sb/intel/bd82x6x, so share a common function between them. Earlier Intel platforms have similar implementations of this function. The common implementation might only need minor alterations to support them. Tested on an ASRock H81M-HDS and Google Peppy (variant of Slippy). No issues arose from this patch. Change-Id: Ife9e3917febf43d8a92cac66b502e2dee8527556 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01sb/intel/common/pciehp.h: Add missing license headerElyes HAOUAS
Change-Id: Ia669b25683c138d96be00db90d01cf406db4c2eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29404 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-24vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logicJoel Kitching
- should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag - implement vboot_platform_is_resuming on platforms missing it - add ACPI_INTEL_HARDWARE_SLEEP_VALUES to two intel southbridges [ originally https://review.coreboot.org/c/coreboot/+/28750 ] BUG=b:114018226 TEST=compile coreboot Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/29060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-22intel: Use CF9 reset (part 1)Patrick Rudolph
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to perform a "system reset" in their hard_reset() implementation. Replace all duplicate CF9 reset implementations for these platforms. Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-20sb/intel/common/firmware: Ensure warning is put lateNico Huber
Change-Id: I400de0a622c2b45ea5ef1f1446f4f489ac397c32 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28673 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-13src/*/intel: introduce warning when building with no IFDAngel Pons
Add a warning as suggested in patch CB:28233 with the "CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED" option. Change-Id: I42b6b336bb519f3d18b5a41eb20b380636ff5819 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-09-13src/*/intel/: clarify Kconfig options regarding IFDStefan Tauner
HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid Inter Flash Descriptor to exist. It does *not* identify platforms or boards that are capable of running in descriptor mode if it's valid. Refine the help text to make this clear. Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply declare that IFD is supported by the platform. Select this value everywhere instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected. Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to the mainboard directory. Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-23Kconfig, Makefile.inc: Remove all traces of ifdfakeAngel Pons
Since ifdfake has been deprecated in favor of better alternatives, there is no need to support it any further. Remove it from the build system. Change-Id: Id62e95ba72004a1e15453e3eb75f09cb8194feb2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28233 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30nb/intel/gm45: Use common code for SMM in TSEGArthur Heymans
This makes i82801ix use the common smm southbridge code to set up smm relocation and smi handler setup. This is needed in this change for the the smm relocation code relies on some southbridge functions provided in the common code. Some of the old code is kept for the Q35 qemu target. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Thinkpad X200: boots and going to and resuming from S3 still works fine. Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23419 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-28sb/intel/gpio: Cache gpiobase in ramstage and romstagePatrick Rudolph
Implement caching like it's done with pmbase. Change-Id: I26d56a9ff1a8d6e64c164f36e23b846b8b459380 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27664 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27sb/intel/common/pmutil: Use new PMBASE APIPatrick Rudolph
Change-Id: I0f37f0c49fd58adafd8a508e806e0f30759a6963 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27287 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27sb/intel/common/smi*: Use new PMBASE APIPatrick Rudolph
Use new PMBASE API functions in common SMI handler. Change-Id: I4c64233ecdb8c1e28b319d84149f34bc8f1e4b97 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-27sb/intel/common: Add functions to manipulate PMBASEPatrick Rudolph
Add common functions to manipulate PMBASE IO window. TODO: * Use the new functions to manipulate register in PMBASE. * Get rid of duplicated get_pmbase() Change-Id: I3b454434ade560fb056b1fc0afe9541df93e14dd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27278 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-16Kconfig: Make the EM100 config option commonSimon Glass
This applied to AMD devices as well as Intel, although the mechanism is different. Move the option to a common place. BUG=b:111363976 TEST=USE=em100-mode emerge-reef coreboot See that a message appears: * Enabling em100 mode (slow SPI flash) Change-Id: Iea437bdf42e7bc49b1d28c812bfc6128e3eb68bd Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-25sb/intel/common/firmware: Enable me_cleaner for NehalemNicola Corna
Recent patches in coreboot have fixed the freeze issues related to the use of me_cleaner on Nehalem. However, at least on the Lenovo X201, with me_cleaner some PCIe devices (like the SATA and USB controllers) disappear. In particular, setting the AltMeDisable bit ("-S" or "-s" flag) makes them disappear completely, while unsetting it makes them disappear only during cold boots. This kind of behaviour was already observed by Youness Alaoui on the Purism Librem laptops ([1]), and it seems related to some required board-specific PCIe configuration in the ME's MFS partition. For this reason, on the Lenovo X201, "-w EFFS" has been added to the me_cleaner arguments, which whitelists the MFS-equivalent partition for ME generation 2. This fixes all the issues, and the PCIe devices work as expected. [1] https://puri.sm/posts/deep-dive-into-intel-me-disablement/ Change-Id: Ie77a80d2cb4945cf1c984bdb0fb1cc2f18e82ebc Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/27178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-21sb/intel/common/rcba_pirq.c: Use common RCBA acces MACROsArthur Heymans
Change-Id: I2fe8d8388cb96e42af4f9be251a41cceeb2e4710 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27042 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21sb/intel/common: Make RCBA manipulation MACROs commonArthur Heymans
No Change in BUILD_TIMELESS. Change-Id: I634526269d45ebdc6c31cdc28d9ec846b397211d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-21Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"Arthur Heymans
In the end it does not look like RCBA register offsets are fully compatible over southbridges. This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4. Is squashed with revert of "sb/intel/common: Fix conflicting OIC register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f. Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-13sb/intel/common/firmware: Use the -S flag of me_cleanerNicola Corna
The -S flag of me_cleaner, in addition to the standard code removal, sets the the AltMeDisable bit (ME 6.x-10.x) or the HAP bit (ME 11.x), which asks Intel ME to stop the execution after the hardware initialization. This should bring some advantages: * The state of Intel ME can be easily obtained by reading the Current Operation Mode register to trigger specific adjustments in the raminit (as already done in bd82x6x) * Intel ME falls into a more defined state, instead of being in a generic "Image Failure" * Hopefully, less code is run by Intel ME, as the execution should stop before even trying to load additional modules Tested on: * Nehalem, Sandy Bridge and Ivy Bridge (Nicola Corna) * Broadwell, Skylake and Kabylake (Youness Alaoui) If needed, the -S flag can be removed or integrated with other board-specific options by overriding CONFIG_ME_CLEANER_ARGS. Change-Id: I2c12d09124dcc39924d1dc4eaf53a2dc1f69a2ac Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/25508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2018-06-11sb/intel/common: Include SPI driver into postcar stageNico Huber
Change-Id: I2ea07cdeb8fc70dbf516831f4da5949fef136b37 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04src/sb/intel/common/spi.c: Adapt and link in romstageArthur Heymans
Based on Nicola Corna's work. This allows for CONFIG_CONSOLE_SPI_FLASH to be used, which writes the console output to the SPI flash. TESTED to still work in ramstage on x220 (correctly writes MRC CACHE), the option CONFIG_CONSOLE_SPI_FLASH compiles for targets using the common Intel SPI code (untested though). Change-Id: I4671653c0b07ab5c4bf91128f18f142ce4f893cf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04sb/intel/common/spi.c: Add a SPI write protect functionArthur Heymans
Could be useful to write protect regions like for instance the MRC_CACHE region. Tested on Intel DG41WV (i82801gx) and Lenovo Thinkpad X220 (bd82x6x) to write protect the mrc_cache region. Change-Id: Id0a9a0de639c5d6761a77a56ceba6d89110a4ea1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-25sb/intel/common/pirq_gen: Rework generating pin-route tablesArthur Heymans
This creates a pin-route matrix first and then generates the ACPI entries based on that. This approach has the advantage of being simpler (no need for checks on double entries) and requiring less access to the pci config space. A few thing that are also fixed: * Don't declare DEFAULT_RCBA redundantly. * Only loop over PCI devices on bus 0 * Add a license header to rcba_pirq.c * Remove inappropriate use of typedefs * Fix the pin field: needs to be a byte * Fix the source field: it should either be a byte or a path (according to Advanced Configuration and Power Interface Specification rev 2.0c) Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22979 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-28src/southbridge: Add spaces around '=='Elyes HAOUAS
Change-Id: Ic81601cef841076a7548ccb3bdf0ed1b5420873e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-23drivers/spi: reduce confusion in the APIAaron Durbin
Julius brought up confusion about the current spi api in [1]. In order alleviate the confusion stemming from supporting x86 spi flash controllers: - Remove spi_xfer_two_vectors() which was fusing transactions to accomodate the limitations of the spi controllers themselves. - Add spi_flash_vector_helper() for the x86 spi flash controllers to utilize in validating driver/controller current assumptions. - Remove the xfer() callback in the x86 spi flash drivers which will trigger an error as these controllers can't support the api. [1] https://mail.coreboot.org/pipermail/coreboot/2018-April/086561.html Change-Id: Id88adc6ad5234c29a739d43521c5f344bb7d3217 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-20pci: Move inline PCI functions to pci_ops.hPatrick Rudolph
Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11Revert "model_206ax: Use parallel MP init"Arthur Heymans
This reverts commit 5fbe788bae15f0d24d56011e8eb8b48c107b7b05. This commit was submitted without its parent being submitted, resulting in coreboot not building. Change-Id: I87497093ccf6909b88e3a40d5f472afeb7f2c552 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-11model_206ax: Use parallel MP initArthur Heymans
This patch adds a few southbridge calls needed for parallel MP init. Moves the smm_relocate() function to smm/gen1/smi.h, since that is where this function is defined now. Tested on Thinkpad X220, shaves of ~30ms on a 2 core, 4 threads CPU. Change-Id: Iacd7bfedfccbc09057e1b7ca3bd03d44a888871d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23432 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06sb/intel/common/firmware: Allow CONFIG_USE_ME_CLEANER on Kaby LakeNicola Corna
Some users have reported a successful boot with me_cleaner on Kaby Lake with OEM firmware: https://github.com/corna/me_cleaner/issues/3 It should work as well on coreboot. Change-Id: Ifc47f19deee5c39ca27b427c9406da7f6e3e9f15 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/25507 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28sb/intel/common: Add common code for SMM setup and smihandlerArthur Heymans
This moves the sandybridge both smm setup and smihandler code to a common place. Tested on Thinkpad X220, still boots, resume to and from S3 is fine so smihandler is still working fine. Change-Id: I28e2e6ad1e95a9e14462a456726a144ccdc63ec9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-03-02sb/intel/common: Fix conflicting OIC register definitionNico Huber
Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location) makes some platforms use the wrong OIC register defi- nition. It was extended to 16-bit in the corporate version of ICH10. So let's give the new size and location a new name: EOIC (extended OIC). This only touches the systems affected by the mentioned change. Other platforms still need to be adapted before they can use the common RCBA definitions. Change-Id: If9e554c072f01412164dc35e0b09272142e3796f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/24924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-02-27sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common locationArthur Heymans
Many generations of Intel hardware have identical code concerning the RCBA. Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-20sb/intel/common: Automatically generate ACPI PIRQTobias Diedrich
Based on change I2b5d68adabf0840162c6f295af8d10d8d3007a34 (sb/intel/common: Add function to automatically generate ACPI PIRQ). This adds functionality to generate PIRQ ACPI tables automatically based on the chipset registers. Mapping of PCI interrupt pin to PIRQ is done by the chipset-specific intel_common_map_pirq() function, an shared implementation of which is provided for the bd82x6x, i82801, i89xx, ibexpeak and lynxpoint chipsets. Example generated _PRT: Scope (\_SB.PCI0) { Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001BFFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001CFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001CFFFF, 0x00000001, 0x00000000, 0x00000015 }, Package (0x04) { 0x001CFFFF, 0x00000002, 0x00000000, 0x00000013 }, Package (0x04) { 0x001DFFFF, 0x00000000, 0x00000000, 0x00000013 }, Package (0x04) { 0x001FFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001FFFFF, 0x00000001, 0x00000000, 0x00000017 }, Package (0x04) { 0x0004FFFF, 0x00000000, 0x00000000, 0x00000010 } }) } Else { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001BFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKF, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000002, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001DFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKH, 0x00000000 }, Package (0x04) { 0x0004FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 } }) } } } Change-Id: Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-10sb/intel/common: Add SOUTHBRIDGE_INTEL_COMMON_SPIArthur Heymans
This introduces a Kconfig option to include common Intel SPI code. Change-Id: I970408e5656c0e8812b8609e2cc10d0bc8d8f6f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-09-27smbus: Fix a typo ("Set the device I'm talking too")Jonathan Neuschäfer
Change-Id: Ia14bbdfe973cec4b366879cd2ed5602b43754260 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-22sb/intel/common/spi.c: Port to i82801gxArthur Heymans
Offsets are a little different. Change-Id: I39199f3279a8b76e290b6693adc50dc2ac0ccf23 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21113 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-10sb/intel/common: Fix HAVE_DEBUG_SMBUSKyösti Mälkki
Failed to build with DEBUG_SMBUS=y, slave_bytes is not initialized until inb(). Change-Id: Ia53717756ed74bc797a9529e36fc6965d6872101 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21470 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-09sb/intel/common: Add HAVE_DEBUG_SMBUSKyösti Mälkki
Change-Id: Ifb1a1eff71968f31af9004ff00717f202d3ec29e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-09sb/intel/common: Fix i2c block commandKyösti Mälkki
Coding style, sync implementation with SMBus counterpart. Change-Id: I75f24e2308de945fc03289636ae914bb87070838 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-09sb/intel/common: Tidy up SMBus block commandsKyösti Mälkki
I forgot to push these changes before merging commit 1b04aa2 sb/intel/common: Fix SMBus block commands Change-Id: I7217f8c0cc78f2161faf31a4c49e3e9515026d15 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-30sb/intel/*: add option to lockdown chipset on normal boot pathBill XIE
On platforms with a PCH, some registers within host bridge should be locked down on each normal boot path (done by either coreboot or payload) and S3 resume (always done by coreboot). A function to perform such locking is implemented in src/northbridge/ intel/*/finalize.c, and is designed as the handler of an #SMI triggered with outb(APM_CNT_FINALIZE, APM_CNT), but currently this #SMI is only triggered during s3 resume, and not on normal boot path. This problem has beed discussed in https://mail.coreboot.org/pipermail/coreboot/2017-August/084924.html . This time, an option "INTEL_CHIPSET_LOCKDOWN" within src/southbridge/ intel/common/Kconfig is added to control the actual locking, which depends on several compatibility flags, including "HAVE_INTEL_CHIPSET_LOCKDOWN". In this commit, "ibexpeak", "bd82x6x", "fsp_bd82x6x", and "lynxpoint" have the flag "HAVE_INTEL_CHIPSET_LOCKDOWN" selected. The change is only well tested on Sandy Bridge, my Lenovo x230. Change-Id: I43d4142291c8737b29738c41e8c484328b297b55 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-20util/me_cleaner: Pull the latest changes from upstreamNicola Corna
Relevant changes (commit 2e8761e): * Add an option to truncate the ME image file * Add full support for Skylake (ME 11) and following, including modules removal, truncation informations and partition relocation * Add two options to generate a shrinked ME image file and the corresponding descriptor with a modified flash layout * Update README.md * Bug fixes Also add a link to the usage guide in the Kconfig help. Change-Id: I690c5d558139f64f38babf3c0988b53834ba8b37 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/20915 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-08-20sb/intel/common: Fix SMBus block commandsArthur Heymans
Clear LAST_BYTE flag at beginning of block commands. For reads, slave device determines in the message format how many bytes it has to transfer out, host firmware only dictates the maximum buffer length. Return SMBUS_ERROR if only partial message was received. For writes, return SMBUS_ERROR if length > 32. For writes, fix off-by-one error reading memory one byte past the buffer end. Change-Id: If9e5d24255a0a03039b52d2863bc278d0eefc311 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-07usbdebug: Refactor early enableKyösti Mälkki
Always sanity check for EHCI class device and move PCI function power enablement up. Change-Id: I1eebe813fbb420738af2d572178213fc660f392a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-07usbdebug: Consolidate EHCI_BAR setupKyösti Mälkki
There is assumption of static EHCI_BAR_INDEX, try to clean it up by bringing BAR programming at one spot. Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-06sb/intel/*: Use common SMBus functionsArthur Heymans
All Intel southbridges implement the same SMBus functions. This patch replaces all these similar and mostly identical implementations with a common file. This also makes i2c block read available to all those southbridges. If the northbridge has to read a lot of SPD bytes sequentially, using this function can reduce the time being spent to read SPD five-fold. Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-25sb/intel/common/gpio: Only set one bit at timePatrick Rudolph
Make sure to set only one bit instead of arbitrary bits set in argument. Change-Id: I39426193d15d8581f79bc2a45c0edb53b19a2cd3 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-16southbridge/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-16sb/intel/common/firmware: Keep CHECK_ME disabled by defaultNaresh G Solanki
While building poppy board, build failed with following error message: Writing new image to build/coreboot.pre.new mv build/coreboot.pre.new build/coreboot.pre util/me_cleaner/me_cleaner.py -c build/coreboot.pre > /dev/null This image does not contains a ME/TXE firmware NR = 0) make: *** [src/southbridge/intel/common/firmware/Makefile.inc:55: add_intel_firmware] Error 1 Hence keeping CHECK_ME unset by default. TEST=Succesfully built coreboot for Poppy & booted to OS. Change-Id: Ib3186498c8da307b686c06c3828e24acbc7f2d17 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicola Corna <nicola@corna.info> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-07src: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-05-24southbridge/intel: Move spi driver to use spi_bus_mapFurquan Shaikh
This is in preparation to get rid of the strong spi_setup_slave implemented by different platforms. BUG=b:38430839 Change-Id: I23c1108c85532b7346ff7e0adb0ac90dbf2bb2cc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-23sb/intel/common: Add common EC fw supportLijian Zhao
Add support to the Intel common firmware Kconfig and Makefile.inc to allow the embedded controller (EC) blob to be added to the final binary through ifdtool. TEST=Add ec.bin and enable in config, build is successful. Change-Id: Ib14732b4d263dde4770bf26b055c005de2540338 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/19719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-19drivers/spi/spi_flash: Move flash ops to spi_flash_ops structureFurquan Shaikh
Define a new spi_flash_ops structure, move all spi flash operations to this structure and add a pointer to this structure in struct spi_flash. BUG=b:38330715 Change-Id: I550cc4556fc4b63ebc174a7e2fde42251fe56052 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-19drivers/spi/spi_flash: Clean up SPI flash probeFurquan Shaikh
1. Rename __spi_flash_probe to spi_flash_generic_probe and export it so that drivers can use it outside spi_flash.c. 2. Make southbridge intel spi driver use spi_flash_generic_probe if spi_is_multichip returns 0. 3. Add spi_flash_probe to spi_ctrlr structure to allow platforms to provide specialized probe functions. With this change, the specialized spi flash probe functions are now associated with a particular spi ctrlr structure and no longer disconnected from the spi controller. BUG=b:38330715 Change-Id: I35f3bd8ddc5e71515df3ef0c1c4b1a68ee56bf4b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-19drivers/spi/spi_flash: Pass in spi_slave structure as const to probe functionsFurquan Shaikh
Pointer to spi_slave structure can be passed in as const to spi flash probe functions since the probe functions do not need to modify the slave properties. BUG=b:38330715 Change-Id: I956ee777c62dbb811fd6ce2aeb6ae090e1892acd Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19707 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-19drivers/spi/spi_flash: Pass in flash structure to fill in probeFurquan Shaikh
Instead of making all SPI drivers allocate space for a spi_flash structure and fill it in, udpate the API to allow callers to pass in a spi_flash structure that can be filled by the flash drivers as required. This also cleans up the interface so that the callers can maintain and free the space for spi_flash structure as required. BUG=b:38330715 Change-Id: If6f1b403731466525c4690777d9b32ce778eb563 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-05drivers/spi: Re-factor spi_crop_chunkFurquan Shaikh
spi_crop_chunk is a property of the SPI controller since it depends upon the maximum transfer size that is supported by the controller. Also, it is possible to implement this within spi-generic layer by obtaining following parameters from the controller: 1. max_xfer_size: Maximum transfer size supported by the controller (Size of 0 indicates invalid size, and unlimited transfer size is indicated by UINT32_MAX.) 2. deduct_cmd_len: Whether cmd_len needs to be deducted from the max_xfer_size to determine max data size that can be transferred. (This is used by the amd boards.) Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19386 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: coreboot org <coreboot.org@gmail.com>
2017-03-19sb/intel/common/firmware: Add Intel ME/TXE firmware checkNicola Corna
Ensure that the provided ME/TXE firmware is valid, using the check capabilities of me_cleaner. me_cleaner checks that the fundamental partition is available and it has a correct signature. The checks performed by me_cleaner aren't exhaustive, but they should find at least whether the user has provided an empty or corrupted firmware. me_cleaner has been tested on all the ME (6-11.6) and TXE (1-3) firmwares available here [1], and it hasn't reported any false positive. [1] http://www.win-raid.com/t832f39-Intel-Engine-Firmware-Repositories.html Change-Id: Ie6ea3b4e637dca4097b9377bd0507e84c4e8f687 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18768 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-02-08southbridge/intel/common/firmware: allow locking ME without HAVE_ME_BINAaron Durbin
The apollolake boards don't have an me.bin proper, but they still have descriptor regions which need to be locked down. Therefore, remove the restriction of HAVE_ME_BIN from LOCK_MANAGEMENT_ENGINE. BUG=chrome-os-partner:62177 TEST=For apollolake one can select LOCK_MANAGEMENT_ENGINE. Change-Id: I73aab3a604ec25cd56d760bf76cc21c5a298799e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18304 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-04sb/intel/common: Hook up me_cleanerNicola Corna
The me_cleaner option is available on multiple platforms: * Sandy and Ivy Bridge (well tested by multiple users). * Skylake and Braswell (tested). * Haswell, Broadwell and Bay Trail (untested). The untested platforms have been included anyways because all the firmwares are very similar and Intel ME/TXE probably behaves in the same way. Change-Id: I46f461a1a7e058d57259f313142b00146f0196aa Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18206 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03sb/intel/common/gpio: Support ICH9M and priorPatrick Rudolph
Write gpio level twice to make sure the level is set after pins have been configred as GPIO and to minimize glitches on newer hardware. Required to set correct GPIO layout on T500. Tested on T500. Change-Id: I691e672c7cb52ca51a80fd29657ada7488db0d41 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18012 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins)
2016-12-23spi: Get rid of SPI_ATOMIC_SEQUENCINGFurquan Shaikh
SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with the ability to perform tx and rx of flash command and response at the same time. Instead of introducing this notion at SPI flash driver layer, clean up the interface to SPI used by flash. Flash uses a command-response kind of communication. Thus, even though SPI is duplex, flash command needs to be sent out on SPI bus and then flash response should be received on the bus. Some specialized x86 flash controllers are capable of handling command and response in a single transaction. In order to support all the varied cases: 1. Add spi_xfer_vector that takes as input a vector of SPI operations and calls back into SPI controller driver to process these operations. 2. In order to accomodate flash command-response model, use two vectors while calling into spi_xfer_vector -- one with dout set to non-NULL(command) and other with din set to non-NULL(response). 3. For specialized SPI flash controllers combine two successive vectors if the transactions look like a command-response pair. 4. Provide helper functions for common cases like supporting only 2 vectors at a time, supporting n vectors at a time, default vector operation to cycle through all SPI op vectors one by one. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17681 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17545 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06spi_flash: Make a deep copy of spi_slave structureFurquan Shaikh
Commit 36b81af (spi: Pass pointer to spi_slave structure in spi_setup_slave) changes the way spi_setup_slave handles the spi_slave structure. Instead of expecting spi controller drivers to maintain spi_slave structure in CAR_GLOBAL/data section, caller is expected to manage the spi_slave structure. This requires that spi_flash drivers maintain spi_slave structure and flash probe function needs to make a copy of the passed in spi_slave structure. This change fixes the regression on Lenovo X230 and other mainboards. Change-Id: I0ad971eecaf3bfe301e9f95badc043193cc27cab Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17728 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Iru Cai <mytbk920423@gmail.com>
2016-12-05spi: Define and use spi_ctrlr structureFurquan Shaikh
1. Define a new structure spi_ctrlr that allows platforms to define callbacks for spi operations (claim bus, release bus, transfer). 2. Add a new member (pointer to spi_ctrlr structure) in spi_slave structure which will be initialized by call to spi_setup_slave. 3. Define spi_claim_bus, spi_release_bus and spi_xfer in spi-generic.c which will make appropriate calls to ctrlr functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Icb2326e3aab1e8f4bef53f553f82b3836358c55e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17684 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Pass pointer to spi_slave structure in spi_setup_slaveFurquan Shaikh
For spi_setup_slave, instead of making the platform driver return a pointer to spi_slave structure, pass in a structure pointer that can be filled in by the driver as required. This removes the need for platform drivers to maintain a slave structure in data/CAR section. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia15a4f88ef4dcfdf616bb1c22261e7cb642a7573 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17683 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Fix parameter types for spi functionsFurquan Shaikh
1. Use size_t instead of unsigned int for bytes_out and bytes_in. 2. Use const attribute for spi_slave structure passed into xfer, claim bus and release bus functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ie70b3520b51c42d750f907892545510c6058f85a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17682 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22spi: Get rid of flash_programmer_probe in spi_slave structureFurquan Shaikh
flash_programmer_probe is a property of the spi flash driver and does not belong in the spi_slave structure. Thus, make spi_flash_programmer_probe a callback from the spi_flash_probe function. Logic still remains the same as before (order matters): 1. Try spi_flash_programmer_probe without force option 2. Try generic flash probing 3. Try spi_flash_programmer_probe with force option If none of the above steps work, fail probing. Flash controller is expected to honor force option to decide whether to perform specialized probing or to defer to generic probing. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I4163593eea034fa044ec2216e56d0ea3fbc86c7d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17465 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22spi: Clean up SPI flash driver interfaceFurquan Shaikh
RW flag was added to spi_slave structure to get around a requirement on some AMD flash controllers that need to group together all spi volatile operations (write/erase). This rw flag is not a property or attribute of the SPI slave or controller. Thus, instead of saving it in spi_slave structure, clean up the SPI flash driver interface. This allows chipsets/mainboards (that require volatile operations to be grouped) to indicate beginning and end of such grouped operations. New user APIs are added to allow users to perform probe, read, write, erase, volatile group begin and end operations. Callbacks defined in spi_flash structure are expected to be used only by the SPI flash driver. Any chipset that requires grouping of volatile operations can select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and define callbacks for chipset_volatile_group_{begin,end}. spi_claim_bus/spi_release_bus calls have been removed from the SPI flash chip drivers which end up calling do_spi_flash_cmd since it already has required calls for claiming and releasing SPI bus before performing a read/write operation. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-08southbridge/intel: Set chipset in ifdtool invocationsAndrey Petrov
Since IFD format is floating, ifdtool needs to be parameterized with a chipset it is dealing with. Add -p <chipset> argument to ifdtool invocations if chipset provides it. Change-Id: I4fd1783b5d994617912aedcf17adc2a98c97227b Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17258 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-16southbridge/intel/common: Add common gpio.cPatrick Rudolph
Add a common southbridge gpio code to reduce existing duplicated code. By adding it to ram-stage, GPIOs can be changed any time, without the need of direct register access. The files are based on bd82x6x and lynxpoint gpio.c. Change-Id: Iaf0c2f941f2625a5547f9cba79da1b173da6f295 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12893 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-10Kconfig: Move defaults for CBFS_SIZEMartin Roth
We want the question for CBFS size to be next to the rom size in the mainboard directory, but that doesn't seem to work for how people want to set the defaults. Instead of having the list of exceptions to the size, just set the defaults at the end of kconfig. - Move the defaults for chipsets not setting HAVE_INTEL_FIRMWARE into the chipset Kconfigs (gm45, nehalem, sandybridge, x4x) - Override the default for HAVE_INTEL_FIRMWARE on skylake. - Move the HAVE_INTEL_FIRMWARE default setting into the firmware Kconfig file - Move the location of the default CBFS_SIZE=ROM_SIZE to the end of the top level kconfig file, while leaving the question where it is. Test=rebuild Kconfig files before and after the change, verify that they are how they were intended to be. Note: the Skylake boards actually changed value, because they were picking up the 0x100000 from HAVE_INTEL_FIRMWARE instead of the 0x200000 desired. This was due to the SOC_INTEL_SKYLAKE being after the HAVE_INTEL_FIRMWARE default. Affected boards were: Google chell, glados, & lars and Intel kunimitsu. Change-Id: I2963a7a7eab037955558d401f5573533674a664f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-10ACPI: Fix IASL Warning about unused method for _OSI checkMartin Roth
According to the ACPI Spec for CondRefOf, the result argument is optional. In all of these locations, it was getting set but not used, creating a warning in new versions of IASL. Since it's an optional argument, just remove it. dsdt.aml 22: if(CondRefOf(\_OSI,Local1)) Warning 3144 - ^ Method Local is set but never used (Local1) Change-Id: I07f49ac5a3708838d1c4a7216dfb11acc415c881 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12692 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-08intel/common/firmware: Add option to configure SPI for EM100Martin Roth
Add a Kconfig option to set the firmware descriptor to allow EM100 use. Change-Id: If5d7cd6ad671f0328ee5be0b5e660dbc837fcac3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12637 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-23southbridge/intel: Move `i82801gx/acpi/platform.asl` to `common/acpi`Paul Menzel
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file in the directory `src/southbridge/intel/i82801gx/acpi`. Devices with the southbridge `intel/i82801ix`, like the laptop Lenovo X200, use the exact same ASL code though. So share this in the directory `src/southbridge/intel/common/acpi`. Change-Id: I33b7993bcdbef7233ed85a683b2858ac72c1d642 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11881 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-29intel: auto include intel/common/firmwareAaron Durbin
Instead of selecting the Kconfig option and adding the subdir entry within each chipset auto include the common/firmware directory as it's guarded by HAVE_INTEL_FIRMWARE. BUG=chrome-os-partner:43462 BRANCH=None TEST=Built glados. Change-Id: I166db67c41b16c4d9f0116abce00940514539fa5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11734 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-07Drop "See file CREDITS..." commentStefan Reinauer
coreboot has no CREDITS file. Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11514 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-04bootstate: remove need for #ifdef ENV_RAMSTAGEAaron Durbin
The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however the current state of the header meant bad build errors in non-ramstage. Therefore, people had to #ifdef in the source. Remove that requirement. Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11492 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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