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2021-02-07sb/intel: Extract `set_global_reset` functionAngel Pons
To avoid duplicating this function in ramstage, factor it out. Change-Id: I64c59a01ca153770481c28ae404a5dfe8c5382d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-06intel: Define `RCBA_LENGTH` in Kconfig and use itAngel Pons
Change-Id: Ief81d49f04c1743b2a37633c4a35da9d6ddb0974 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50039 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05intel: Turn `DEFAULT_RCBA` into a Kconfig symbolAngel Pons
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases where a pointer cast would be necessary. Instances in Sandy Bridge MRC code were left as-is intentionally, so as not to collide with another cleanup patch train. Tested with BUILD_TIMELESS=1, these boards remain identical: - Asus P8Z77-V LX2 - Packard Bell MS2290 Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01sb/intel/common/rcba.h: Guard RCBAx macro parametersAngel Pons
Add brackets around the parameters to avoid operation order problems. Change-Id: I689983b5b937f66b1a520eea61a38fb96c13c007 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50035 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28southbridge/intel: Define default value for ME_REGION_ALLOW_CPU_READ_ACCESSSridhar Siricilla
The patch defines default value for ME_REGION_ALLOW_CPU_READ_ACCESS config. It sets value 'y' if CSE Lite SKU is integrated, otherwise value 'n'. The config ME_REGION_ALLOW_CPU_READ_ACCESS ensures host has read access to ME region when the LOCK_MANAGEMENT_ENGINE is enabled and CSE Lite SKU is integrated. TEST=Verified build for JSL Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I680a23e27ae2bf4d85bf919134c47882f308af56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49891 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-26sb,soc/intel: Refactor power_on_after_fail optionKyösti Mälkki
It's only necessary to call get_option() with SLP_TYP S5. Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49251 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25sb,soc/intel: Remove no-op APMC for C-state and P-stateKyösti Mälkki
Change-Id: I3c1aa7f68eb03f04ddb9c1a5e960e3e2050a029c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49250 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25sb/intel/common: Change some SMI loggingKyösti Mälkki
Change-Id: Ief0c3d36e6de6e18b7f2613f043ac4d31a193f9d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49249 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25cpu/x86/smm: Use common APMC loggingKyösti Mälkki
Unify the debug messages on raised SMIs. Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49248 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15build system: Remove flock calls from intermediate processingPatrick Georgi
Now that intermediate coreboot.pre manipulation is serialized within the build system, remove the flock calls. Change-Id: I8a767918aec5fcb7127ebb19ac46e58bed7967fb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-15nb/intel/pineview: Extract HPET setup and delay functionAngel Pons
To allow other platforms to reuse this code, extract it into a separate compilation unit. Since HPET is enabled through the southbridge, place the code in the southbridge scope. Finally, select the newly-added Kconfig option from i82801gx and replace lpc.c `enable_hpet` function. Change-Id: I7a28cc4d12c6d79cd8ec45dfc8100f15e6eac303 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-14build system: Structure and serialize INTERMEDIATEPatrick Georgi
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying the file in some way. When running them in parallel, coreboot.pre can be read from and written to in parallel which can corrupt the result. Add a function to create those rules that also adds existing INTERMEDIATE targets to enforce an order (as established by evaluation order of Makefile.inc files). While at it, also add the addition to the PHONY target so we don't forget it. BUG=chromium:1154313, b:174585424 TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2 timeout and sercon) and saw that they were executed. Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08*/Makefile.inc: Add some INTERMEDIATE targets to .PHONYArthur Heymans
Change-Id: I125e40204f3a9602ee5810d341ef40f9f50d045b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48897 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08cbfstool: Use flock() when accessing CBFS filesJulius Werner
Trying to do multiple operations on the same CBFS image at the same time likely leads to data corruption. For this reason, add BSD advisory file locking (flock()) to cbfstool (and ifittool which is using the same file I/O library), so that only one process will operate on the same file at the same time and the others will wait in line. This should help resolve parallel build issues with the INTERMEDIATE target on certain platforms. Unfortunately, some platforms use the INTERMEDIATE target to do a direct dd into the CBFS image. This should generally be discouraged and future platforms should aim to clearly deliminate regions that need to be written directly by platform scripts with custom FMAP sections, so that they can be written with `cbfstool write`. For the time being, update the legacy platforms that do this with explicit calls to the `flock` utility. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I022468f6957415ae68a7a7e70428ae6f82d23b06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-04arch/x86: Pass GNVS as parameter to SMM moduleKyösti Mälkki
Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14sb/intel/common/smbus_ops.c: Clean up read resourcesAngel Pons
Using `pci_dev_read_resources` works just as well on bd82x6x (the allocator does the same) and allows dropping the i82801gx check. Change-Id: I1cb05131a82ebb7c45827eff8e09e445d9c695b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48538 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11sb/intel/x/smbus.c: Factor out common codeAngel Pons
Since common smbus.c gets built for romstage as well, create a new file to hold this common code. Account for ICH7 not having a memory BAR, too. Change-Id: I4ab46750c6fb7f71cbd55848e79ecc3e44cbbd04 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48364 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-07sb/intel/common: Modify CONFIG_LOCK_MANAGEMENT_ENGINE behaviorSridhar Siricilla
The patch modifies KConfig behaviour if CSE Lite SKU is integrated into the coreboot. When the CSE Lite SKU is integrated, the KConfig prevents writing to ME region but keeps read access enabled. Since CSE Lite driver checks the signature of RW partition to identify the interrupted CSE firmware update, so host must have read access to the ME region. Also, the patch modifies the KConfig's help text to reflect the change. When CSE Lite SKU is integrated, master access permissions: FLMSTR1: 0x002007ff (Host CPU/BIOS) EC Region Write Access: disabled Platform Data Region Write Access: disabled GbE Region Write Access: disabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: disabled EC Region Read Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: disabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled BUG=b:174118018 TEST=Built and verified the access permissions. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2f6677ab7b59ddce827d3fcaae61508a30dc1b28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2020-11-04sb/intel/common/acpi/pcie.asl: Generalise file commentAngel Pons
This file is no longer specific to 6 and 7 series PCHs. Change-Id: Ib89378bd6ba1d80281b92a79d37b9fdeaaed40fb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46762 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04sb/intel/common/acpi/irqlinks.asl: Clean up cosmeticsAngel Pons
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I8562fc3278144380b0ab842d88176114821be823 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46760 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26src: Include <arch/io.h> when appropriateElyes HAOUAS
Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21src/southbridge: Drop unneeded empty linesElyes HAOUAS
Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-08-17src: Use PCI_BASE_ADDRESS_* macros instead of magic numbersElyes HAOUAS
Change-Id: Id3390c5ac6a9517ffc2d202f41802e6f4d2e314c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44371 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26southbridge/intel/common: Replace outb with post_code in finalize.cSindhoor Tilak
The outb() call is replaced with the post_code() The post_codes.h is replaced with console.h since console.h includes both the post_code definition and post_codes.h Change-Id: I21345260e86de30614c416e2f509bd77b9e00cb7 Signed-off-by: Sindhoor Tilak <sindhoor@sin9yt.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-21ironlake/ibexpeak: Move early_smbus.c to common codeAngel Pons
We will update the other platforms to use this common code in susbsequent commits. While we are at it, reflow a broken line, define the SMBus PCI device in the header and fix whitespace. Change-Id: I1fdff2feead4165f02b24cb948d8c03318969014 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41999 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASEAngel Pons
Make it default to 0x400, which is what the touched southbridges use. Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-12sb/intel/common/acpi/irqlinks.asl: Add missing IRQsAngel Pons
IRQ 10 and IRQ 11 are valid for all southbridges using this code, as per their respective datasheets. So, add them for the sake of completeness. Change-Id: Ib4504861ed316a95b9735e0ed79f108f18071b3b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43158 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08sb/intel: Factor out irqlinks.aslAngel Pons
Files are identical for all southbridges, except bd82x6x. We will take care of that in subsequent commits. Change-Id: I38e5d440e188d26f8997bc22a956187b728487ca Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43157 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08sb/intel: Factor out ICH ACPI for HDAAngel Pons
Files are identical between all three southbridges, and differ for PCH. Change-Id: Ic6a926af675bda3db3a5795df9e8f490caf3ebf4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43156 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06src/**/acpi/smbus.asl: Drop dead codeAngel Pons
The `ENABLE_SMBUS_METHODS` symbol is not defined anywhere, so this code isn't even being tested. So, throw it into the bitbucket before it rots any further. If anyone needs that code ever again, it's in git history. Change-Id: I22e3f1ad54e81f811c9660d54f3765f3c6b83f01 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-27sb/intel/common: Add early SPI codeAngel Pons
All Intel southbridges with SPI perform this write. Put it inside a function in common code. Use a different name to avoid a name clash. As it is only one statement, make it inline so that it can be defined on the header itself. It is only called once per southbridge anyway. Change-Id: I3c284d6cffd22949d50b4c4f9846ceaef38d7cda Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-24ACPI: Replace smm_setup_structures()Kyösti Mälkki
Except for whitespace and varying casts the codes were the same when implemented. Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS. Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-16sb/intel/common/pmutil: Add dump_all_status()Kyösti Mälkki
Change-Id: I10582941afd68425603f6c4cadd228797cd098e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16sb,soc/intel: Replace smm_southbridge_enable_smi()Kyösti Mälkki
Change-Id: I8a2e8b0c104d9e08f07aeb6a2c32106480ace3e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16sb/intel: Clean up some SMI enablesKyösti Mälkki
Change-Id: I191ad709fd3c6f906cd34b0053eeaebdb80d410d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-14southbridge/intel/common: Introduce ASL2.0 syntaxAlexey Buyanov
Modify southbridge/intel/common .asl files to comply with ASL2.0 syntax for better code readability and clarity BUG=none BRANCH=none TEST= Google Parrot platform coreboot binary remains the same after the changes are applied Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com> Change-Id: Ia11769d5ac6154ed79d967d7bab36e12a1db751a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42084 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06src: Remove unused '#include <cpu/x86/smm.h>'Elyes HAOUAS
Change-Id: I1632d03a7a73de3e3d3a83bf447480b0513873e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41685 Reviewed-by: David Guckian Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12southbridge/intel/common: Add Process CallChristian Walter
Add functionality to use process call cycle. It can be used to write/read data to/from e.g. EEPROM attached to SMBus Controller via I2C. Tested on: * C246 Change-Id: Ifdac6cf70a4ce744601f5d152a83d2125ea88360 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39875 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12Revert "sb/intel/common/acpi: Add more Windows versions"Nico Huber
This reverts commit cc805d9dd64ca2d3c8de2b2de2ea7c53b387ff8f. Advertising certain Windows versions triggers different paths in the OS. As there may also be device specific quirks in the OS, such changes need to be tested thoroughly on all affected devices. There was at least one very subtle regression introduced by this. When Linux sees "Windows 2012" support advertised, it disables the `acpi_video` backlight controls, at least on devices with Intel IGD. Without user-space handling the ACPI events, keyboard backlight controls stop working. Moreover, the commit message didn't state any reason for this change. Why was it merged? Change-Id: I722075f8e8f836b039fb8b8277e665fb49dac8f4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08southbridge/*/Kconfig: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS
Change-Id: I339b455683ad481720b67a322bf51c891c2b611d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41142 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: move copyrights and authors to AUTHORSPatrick Georgi
Also split "this is part of" line from copyright notices. Change-Id: Ibc2446410bcb3104ead458b40a9ce7819c61a8eb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01sb/common/smihandler: Fix 16-bit read/write to PCI_COMMAND registerElyes HAOUAS
Change-Id: Ib403f5a231f86bdc60b956e72a4ae631aa6a3899 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-05-01sb/intel/common/{madt,rcba_pirq}.c: Convert to 96 characters line lengthElyes HAOUAS
Change-Id: I62a213013d9008d8a4a22b5908b7fc7d1b663c4b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01src: Remove unused 'include <cpu/x86/cache.h>'Elyes HAOUAS
Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40666 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to acpi_fill_ssdt()Furquan Shaikh
.acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28security: Add common boot media write protectionPatrick Rudolph
Introduce boot media protection settings and use the existing boot_device_wp_region() function to apply settings on all platforms that supports it yet. Also remove the Intel southbridge code, which is now obsolete. Every platform locks the SPIBAR in a different stage. For align up with the common mrc cache driver and lock after it has been written to. Tested on Supermicro X11SSH-TF. The whole address space is write-protected. Change-Id: Iceb3ecf0bde5cec562bc62d1d5c79da35305d183 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-04-04src/southbridge: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I5b00b3e38edda90f35f0679cd4171a3499288f24 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-31security/vboot: relocate and rename vboot_platform_is_resuming()Bill XIE
After measured boot is decoupled from verified boot in CB:35077, vboot_platform_is_resuming() is never vboot-specific, thus it is renamed to platform_is_resuming() and declared in bootmode.h. Change-Id: I29b5b88af0576c34c10cfbd99659a5cdc0c75842 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15nb/intel/nehalem: Rename to ironlakeAngel Pons
The code is for Arrandale CPUs, whose System Agent is Ironlake. This change simply replaces `nehalem` with `ironlake` and `NEHALEM` with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as changing some of them would impact the resulting binary. Tested with BUILD_TIMELESS=1 without adding the configuration options into the binary, and packardbell/ms2290 does not change. Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06sb/intel/common/firmware/Makefile.inc: use ifdtool --output flagMarcello Sylvester Bauer
Use the ifdtool --output flag to modify coreboot.pre inplace, instead of using the `mv` command to get the same result. In this way the stdout will make more sense in the build context. Change-Id: I6dacc8b39052801c770c02fa2aa1b526747ae496 Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-01sb/intel/common/acpi: Add more Windows versionsPeter Lemenkov
For the up-to-date list of Windows versions follow this link: https://docs.microsoft.com/en-us/windows-hardware/drivers/acpi/winacpi-osi Change-Id: I5ee724f0b03edbfff7dd5b2ae642020cbcbab6d2 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37943 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-28drivers/spi/spi_flash: remove spi flash namesAaron Durbin
The names of each spi flash cause quite a bit of bloat in the text size of each stage/program. Remove the name entirely from spi flash in order to reduce overhead. In order to pack space as closely as possible the previous 32-bit id and mask were split into 2 16-bit ids and masks. On Chrome OS build of Aleena there's a savings of >2.21KiB in each of verstage, romstage, and ramstage. Change-Id: Ie98f7e1c7d116c5d7b4bf78605f62fee89dee0a5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-01-22{soc,southbridge}/*/*/acpi: Add possibility to disable S4Wim Vervoorn
Some boards don't support S3 or S4. The S4 state can't be removed from the available sleep states. Add a config item that allows removal of the S4 state from the list of available sleep states. The S4 state can be removed by selecting the item on board level. For the AMD chipsets the SSFG mask is updated to remove the S4 state. BUG=N/A TEST=build Change-Id: Id802c4cc40308ddf39e99e7f226d55e0e020f0c9 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38431 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-12sb/intel/common: Move SMBus register layout outside headerKyösti Mälkki
Change-Id: I841cc3bd636414c59af15d64d3f96b9be158af98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09sb/intel/common: Add smbus_set_slave_addr()Kyösti Mälkki
Change-Id: I7dddb61fab00e0f4f67d4eebee0cfe8dcd99f4ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38230 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09sb/intel/common: Add smbus_host_reset()Kyösti Mälkki
Change-Id: I3f6000df391295e2c0ce910a2a919a1dd3333519 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09sb/intel/common: Rename smbus_base to baseKyösti Mälkki
Change-Id: I163c82270d2360fea6c11d9270aad6dddc02e68c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09device,sb/intel: Move SMBus host controller prototypesKyösti Mälkki
Also change some of the types to match the register widths of the controller. It is expected that these prototypes will be used with SMBus host controllers inside AMD chipsets as well, thus the change of location. Change-Id: I88fe834f3eee7b7bfeff02f91a1c25bb5aee9b65 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38226 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09sb/intel/common: Change some local SMBus function signaturesKyösti Mälkki
Change-Id: I82be883e08ca58fa454b4ad73d20dde2d40a8e3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09sb/intel/common: Add SMBUS register read-modify-writeKyösti Mälkki
Change-Id: Ibe967d02fd05f4a8f643a5c5b17885701946d1c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09sb/intel/common: Wrap inb/outb()Kyösti Mälkki
On Intel, accessing the SMBus register banks can be done via IO and, since at least ICH10, via MMIO. We may want to use the latter in the future. Change-Id: I67fcbc7b6f6be61c93bc608e556a577ef9e52325 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09sb/intel/common: Add smbus_{read/write}_word() variantsKyösti Mälkki
Change-Id: I1a9432c901e7baa545d34c1d0f82212bf59f8e23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38141 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09drivers/pc80/rtc: Separate {get|set}_option() prototypesKyösti Mälkki
Long-term plan is to support loading runtime configuration from SPI flash as an alternative, so move these prototypes outside pc80/. Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-03spi-generic: remove SPI_FLASH_SECTOR_ERASE_TIMEOUT_MSAaron Durbin
There was one user of SPI_FLASH_SECTOR_ERASE_TIMEOUT_MS, southbridge/intel/common/spi.c. Remove the define and encode the 1 second timeout that it was wanting at the single use site. Change-Id: If33a1a04bc4d3441e90bf0ca305ddf71c4f8bb88 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-12-20{drivers,southbridge}: Replace min() with MIN()Elyes HAOUAS
This is to remove min/max() from <stdlib.h>. Change-Id: Ica03d9aec8a81f57709abcac655dfb0ebce3f8c6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37818 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19src/southbridge: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I5728b44fdd680b21e951397a2390e24f9171ac34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32829 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02src/: Remove g_ prefixes and _g suffixes from variablesPatrick Georgi
These were often used to distinguish CAR_GLOBAL variables that weren't directly usable. Since we're getting rid of this special case, also get rid of the marker. This change was created using coccinelle and the following script: @match@ type T; identifier old =~ "^(g_.*|.*_g)$"; @@ old @script:python global_marker@ old << match.old; new; @@ new = old if old[0:2] == "g_": new = new[2:] if new[-2:] == "_g": new = new[:-2] coccinelle.new = new @@ identifier match.old, global_marker.new; @@ - old + new @@ type T; identifier match.old, global_marker.new; @@ - T old; + T new; @@ type T; identifier match.old, global_marker.new; @@ - T old + T new = ...; There were some manual fixups: Some code still uses the global/local variable naming scheme, so keep g_* there, and some variable names weren't completely rewritten. Change-Id: I4936ff9780a0d3ed9b8b539772bc48887f8d5eed Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-29sb/intel/spi: Drop CAR_GLOBAL_MIGRATIONArthur Heymans
Change-Id: I693cf494522c3bc1e1697a09be3e98fcb6db634d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-26southbridge/intel/common/spi.c: Define __SIMPLE_DEVICE__Arthur Heymans
This simplifies PCI config space accessors. Change-Id: Idf0f90ee2dc1dcb0003ef5d56eff44ca9a5634e7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-26sb/intel/common/spi: Add Baytrail/Braswell supportArthur Heymans
The mechanism for getting the SPIBAR is little different. Tested on Intel Minnowboard Turbot. Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-21nb/sb/cpu: Drop Intel Rangeley supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I41589118579988617677cf48af5401bc35b23e05 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-18sb/intel/common: Properly guard USB debugArthur Heymans
The declarations in usb_debug.c needs to be guarded in order to not conflict with other chipsets. Change-Id: I84c3401b9419f2878c2cfdf81147fa854018f9ae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36878 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15nb/intel/i945: Initialize console in bootblockArthur Heymans
Change-Id: Ic6ea158714998195614a63ee46a057f405de5616 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-10sb/intel/common: Remove the SOUTHBRIDGE_INTEL_COMMON Kconfig symbolArthur Heymans
All code in southbridge/intel/common is now properly guarded by a Kconfig symbol, making SOUTHBRIDGE_INTEL_COMMON obsolete. Change-Id: Ifeccfaa9534f903e3f3543e1f9f3d5f3345b461e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36438 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-10sb/intel/common: Make COMMON_RESET optionalArthur Heymans
Change-Id: Id706919835100903dd4ebac2bbd2f3a44c2b6b60 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-11-10sb/intel/common: Make linking rtc.c conditionalArthur Heymans
Change-Id: I7321da453c0d9bb4a142c3c93103d8dc0ff416b7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-09arch/x86: Replace some __SMM__ guardsKyösti Mälkki
We generally do not guard source in attempts to reduce the final object sizes, but rely on garbage collection. Most of the __unused attributes inserted here will be removed when remaining __SIMPLE_DEVICE__ guards can be removed. Change-Id: I2440931fab4f41d7e8249c082e6c9b5a9cd0ef13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36641 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09ELOG: Introduce elog_gsmi variantsKyösti Mälkki
This avoids a lot of if (CONFIG(ELOG_GSMI)) boilerplate. Change-Id: I87d25c820daedeb33b3b474a6632a89ea80b0867 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36647 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04sb/intel/common/platform.asl: Remove setting unused GNVSArthur Heymans
Change-Id: I842af0a0e6435d33759649065b2b5a6f6d35071d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04sb/intel: Move 'smbus.asl' to common placeElyes HAOUAS
Change-Id: Ia5b148c54224269bda98afe7c8a2c22c10a3bf56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-01soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpiSubrata Banik
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to refer sleepstates.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS. Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30sb/intel/common: Make linking pmbase.c conditionalArthur Heymans
Change-Id: I6a7cd96699dbeb42a53bf1d25db1bcf93e416e0f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33200 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30sb/intel/common/Makefile: Use 'all' class to link files in all stagesArthur Heymans
This links the reset function, the common pmbase functions and the spi driver in all stages. The RTC code is not included in SMM as it is unused there. Change-Id: I65926046d941df3121c7483d69c0b4f7003d783e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-30src/southbridge: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iee2056a50a1201626fa29194afdbfc1f11094420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36333 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-22sb/intel/common/smihandler: Fix compilation on x86_64Patrick Rudolph
Use uintptr_t instead of uint32_t to fix compilation on x86_64. Change-Id: I5584f849202c0a833c751a80bdd9a8f86c60169a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36172 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-03southbridge/intel: Add config option to validate firmware descriptorMathew King
Add new config option to validate the Intel firmware descriptor against the fmap layout. This will prevent a firmware descriptor from being used that could corrupt regions of the bootimage in certian circumstances. BUG=chromium:992215 TEST=Build firmware image with mismached decriptor and fmp Without VALIDATE_INTEL_DESCRIPTOR set firmware builds With VALIDATE_INTEL_DESCRIPTOR set error is shown with mismached regions Change-Id: I9e8bb20485e96026cd594cf4e9d6b11b2bf20e1f Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-02sb/intel/common/smihandler: Hook up smmstoreArthur Heymans
TESTED on Asus P5QC. Change-Id: I20b87f3dcb898656ad31478820dd5153e4053cb2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30012 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30sb/intel/spi: Use different SPIOPS for most SST flashesArthur Heymans
Many supported SST flashes use the AAI OP (0xad) to write. TESTED on Thinkpad X60 with SST25VF016B, flashrom can use AAI_WRITE op with locked down SPIOPS. Change-Id: Ica72eda04a8d9f4e563987871b1640565c6e7e12 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-25soc/fsp_broadwell_de: fix flashconsole support for platformMatt DeVillier
CB:29633 switched platform to use sb/common spi implementation, which worked until CAR_GLOBAL was removed in CB:30506. Revert the changes back to usage of CAR_GLOBAL in the common spi driver so that flashconsole will work again in romsatge for fsp_broadwell_de. Test: verify flashconsole functional on out-of-tree Broadwell-DE board Change-Id: I72e5db1583199b5ca4b6ec54661282544d326f0f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-20sb/intel/common/fw: Make make aware that it needs binariesNico Huber
As we redirect all `dd` output to /dev/null (it would clutter the console otherwise), there is no error message if a binary to be added isn't found. If we add them as dependency, OTOH, `make` will complain properly. Change-Id: I40c3979b84341cb88c7e9a5084c1a97230ea5503 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33327 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12southbridge: Remove not used #include <elog.h>Elyes HAOUAS
Change-Id: Ifa88e3fd824ec57c21de5967e1634c8823fe0fbb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33730 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20src: Remove variable length arraysJacob Garber
Variable length arrays were a feature added in C99 that allows the length of an array to be determined at runtime. Eg. int sum(size_t n) { int arr[n]; ... } This adds a small amount of runtime overhead, but is also very dangerous, since it allows use of an unlimited amount of stack memory, potentially leading to stack overflow. This is only worsened in coreboot, which often has very little stack space to begin with. Citing concerns like this, all instances of VLA's were recently removed from the Linux kernel. In the immortal words of Linus Torvalds [0], AND USING VLA'S IS ACTIVELY STUPID! It generates much more code, and much _slower_ code (and more fragile code), than just using a fixed key size would have done. [...] Anyway, some of these are definitely easy to just fix, and using VLA's is actively bad not just for security worries, but simply because VLA's are a really horribly bad idea in general in the kernel. This patch follows suit and zaps all VLA's in coreboot. Some of the existing VLA's are accidental ones, and all but one can be replaced with small fixed-size buffers. The single tricky exception is in the SPI controller interface, which will require a rewrite of old drivers to remove [1]. [0] https://lkml.org/lkml/2018/3/7/621 [1] https://ticket.coreboot.org/issues/217 Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-30 22:04:35 +0000