coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2018-06-21	sb/intel/common/rcba_pirq.c: Use common RCBA acces MACROs	Arthur Heymans
	Change-Id: I2fe8d8388cb96e42af4f9be251a41cceeb2e4710 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27042 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21	Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"	Arthur Heymans
	In the end it does not look like RCBA register offsets are fully compatible over southbridges. This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4. Is squashed with revert of "sb/intel/common: Fix conflicting OIC register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f. Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-25	sb/intel/common/pirq_gen: Rework generating pin-route tables	Arthur Heymans
	This creates a pin-route matrix first and then generates the ACPI entries based on that. This approach has the advantage of being simpler (no need for checks on double entries) and requiring less access to the pci config space. A few thing that are also fixed: * Don't declare DEFAULT_RCBA redundantly. * Only loop over PCI devices on bus 0 * Add a license header to rcba_pirq.c * Remove inappropriate use of typedefs * Fix the pin field: needs to be a byte * Fix the source field: it should either be a byte or a path (according to Advanced Configuration and Power Interface Specification rev 2.0c) Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22979 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-27	sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location	Arthur Heymans
	Many generations of Intel hardware have identical code concerning the RCBA. Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-20	sb/intel/common: Automatically generate ACPI PIRQ	Tobias Diedrich
	Based on change I2b5d68adabf0840162c6f295af8d10d8d3007a34 (sb/intel/common: Add function to automatically generate ACPI PIRQ). This adds functionality to generate PIRQ ACPI tables automatically based on the chipset registers. Mapping of PCI interrupt pin to PIRQ is done by the chipset-specific intel_common_map_pirq() function, an shared implementation of which is provided for the bd82x6x, i82801, i89xx, ibexpeak and lynxpoint chipsets. Example generated _PRT: Scope (\_SB.PCI0) { Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001BFFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001CFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001CFFFF, 0x00000001, 0x00000000, 0x00000015 }, Package (0x04) { 0x001CFFFF, 0x00000002, 0x00000000, 0x00000013 }, Package (0x04) { 0x001DFFFF, 0x00000000, 0x00000000, 0x00000013 }, Package (0x04) { 0x001FFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001FFFFF, 0x00000001, 0x00000000, 0x00000017 }, Package (0x04) { 0x0004FFFF, 0x00000000, 0x00000000, 0x00000010 } }) } Else { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001BFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKF, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000002, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001DFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKH, 0x00000000 }, Package (0x04) { 0x0004FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 } }) } } } Change-Id: Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>