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Implement caching like it's done with pmbase.
Change-Id: I26d56a9ff1a8d6e64c164f36e23b846b8b459380
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27664
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make sure to set only one bit instead of arbitrary bits set in argument.
Change-Id: I39426193d15d8581f79bc2a45c0edb53b19a2cd3
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Write gpio level twice to make sure the level is set
after pins have been configred as GPIO and to minimize
glitches on newer hardware.
Required to set correct GPIO layout on T500.
Tested on T500.
Change-Id: I691e672c7cb52ca51a80fd29657ada7488db0d41
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18012
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
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Add a common southbridge gpio code to reduce existing
duplicated code.
By adding it to ram-stage, GPIOs can be changed any time,
without the need of direct register access.
The files are based on bd82x6x and lynxpoint gpio.c.
Change-Id: Iaf0c2f941f2625a5547f9cba79da1b173da6f295
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12893
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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