coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2012-11-14	SMM: Pass the ACPI GNVS pointer via state save map	Duncan Laurie
	Instead of hijacking some random memory addresses to relay the GNVS pointer to SMM we can use EBX register during the write to APM_CNT register when the SMI is triggered. Change-Id: I79a89512c40353d72ad058cbf2e6a23a696945da Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1766 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-07	SMI: Change order of SMI_EN and PM1_EN init	Duncan Laurie
	This appears to fix an infrequent resume hang on Ivybridge. Tested on 2 devices with 15k suspend/resume cycles each Change-Id: I53618bc7966824413f1720a2be3cbd2550e29473 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1704 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-07-25	ELOG: Log boot-time events found in southbridge	Duncan Laurie
	This is called from the SMI handler install because those setup functions clear many of these registers. Ensure that these events show up in the log as appropriate. Example log output: 159 \| 2012-06-23 14:31:54 \| SUS Power Fail 160 \| 2012-06-23 14:31:54 \| System Reset 161 \| 2012-06-23 14:31:54 \| ACPI Wake \| S5 Change-Id: I48c423c10ee7e6c2829bcc95f6cfabb4979c25a9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1319 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04	Add support for Intel Panther Point PCH	Stefan Reinauer
	Change-Id: Iac3cd25b36493bb203e849674320e113cc5fce32 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/853 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>