coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2017-06-27	sb/intel/bd82x6x: Fill in acpi_name	Patrick Rudolph
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-09-02	southbridge/bd82x6x: use new ssdt sata port generator	Alexander Couzens
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-02-15	x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer	Kevin Paul Herbert
2014-07-08	southbridge: Trivial - drop trailing blank lines at EOF	Edward O'Callaghan
2014-01-12	ibexpeak / bd82x6x: Make SATA mode user-visible option.	Vladimir Serbinenko
2013-03-17	bd82x6x: Add config option to force SATA link to different speeds.	Shawn Nematbakhsh
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-08-04	Perform additional programming requirements for SATA	Stefan Reinauer
2012-07-26	SATA: Add option to configure gen3 transmitter	Duncan Laurie
2012-07-24	bd82x6x: Convert all PCI ID lists to new scheme	Stefan Reinauer
2012-05-01	Fix SATA port map to only enable port 0	Stefan Reinauer
2012-05-01	Allow device ID arrays in the PCI driver structure	Vadim Bendebury
2012-04-04	Add support for Intel Panther Point PCH	Stefan Reinauer