coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2017-07-16	southbridge/intel: add IS_ENABLED() around Kconfig symbol references	Martin Roth
2016-12-06	intel PCI ops: Remove explicit PCI MMCONF access	Kyösti Mälkki
2016-08-31	src/southbridge: Code formating	Elyes HAOUAS
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-06-04	devicetree: Discriminate device ops scan_bus()	Kyösti Mälkki
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-02-15	x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer	Kevin Paul Herbert
2014-12-02	Replace hlt with halt()	Patrick Georgi
2014-06-21	intel boards: Use acpi_is_wakeup_s3()	Kyösti Mälkki
2013-08-09	intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses	Kyösti Mälkki
2013-07-10	Drop some duplicates of PCI-e config functions	Kyösti Mälkki
2013-03-22	x86: Unify arch/io.h and arch/romcc_io.h	Stefan Reinauer
2012-11-08	elog: add extended management engine event	Duncan Laurie
2012-07-26	Log event for abnormal management engine status	Duncan Laurie
2012-07-26	ME: Move ME v8 lockdown to finalize step	Duncan Laurie
2012-07-24	Fix automatic ME detection in finalize	Stefan Reinauer
2012-07-24	Cougar/Panther Point: Compile in ME7 and ME8 code at the same time	Stefan Reinauer
2012-07-24	Fix ME hash functions on Panther Point/Cougar Point	Stefan Reinauer
2012-04-04	Add support for Intel Panther Point PCH	Stefan Reinauer