coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2014-07-08	southbridge: Trivial - drop trailing blank lines at EOF	Edward O'Callaghan
2014-06-21	intel boards: Use acpi_is_wakeup_s3()	Kyösti Mälkki
2013-06-03	Intel BD82x6x: LPC: Unify I/O APIC setup	Paul Menzel
2013-04-16	Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2	Vladimir Serbinenko
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-07-26	Reserve bd82x6x LPC decode ranges in the resource allocator	Marc Jones
2012-07-25	ELOG: Log boot-time events found in southbridge	Duncan Laurie
2012-07-25	CougarPoint/PantherPoint: Add HM77 device ID to table	Kimarie Hoot
2012-07-24	Add specific power management init code for PantherPoint	Duncan Laurie
2012-07-24	bd82x6x: Convert all PCI ID lists to new scheme	Stefan Reinauer
2012-07-24	Add support for HM70 and NM70 LPC bridge	Stefan Reinauer
2012-05-01	Don't disable ACPI in the S3 resume path	Duncan Laurie
2012-05-01	add new LPC controller device ID value	Vadim Bendebury
2012-04-04	Add support for Intel Panther Point PCH	Stefan Reinauer