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2018-01-24AGESA f15 cimx/sb700: Remove unused chips codeKyösti Mälkki
Change-Id: Id4e05941122c8756f15d5d24482e4cdc04215c55 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-24amd/torpedo cimx/sb900: Fix include directoryKyösti Mälkki
Change-Id: Ie472092f8926231f4e1bd1fb12839b532b4ad158 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23AGESA_LEGACY: Apply final cleanup and file removalsKyösti Mälkki
With no boards left using AGESA_LEGACY, wipe out remains of that everywhere in the tree. Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17AGESA f15 boards: Remove - using LATE_CBMEM_INITKyösti Mälkki
Boards that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. Removed boards: amd/dinar tyan/s2886 supermicro/h8scm supermicro/h8qgi Change-Id: I16be3b43fc0c48d58ed8b6667880c9571c6f5510 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-15AMD GX2 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/amd/geode_gx2 northbridge/amd/gx2 southbridge/amd/cs5535 Mainboards: mainboard/amd/rumba mainboard/lippert/frontrunner mainboard/wyse/s50 Change-Id: I81c130f53bbfa001edbfdb7a878ef115757f620c Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-14AMD CIMx SB800: late.c: Use variable `device` from for loop conditionPaul Menzel
Use the variable `device` instead of `dev` in the predicate of the if condition, as `dev` is not changed in the for loop. The for loop was added in the following commit. commit 8fed77ae4c46122859d0718678e54546e126d4bc Author: Scott Duplichan <scott@notabs.org> Date: Sat Jun 18 10:46:45 2011 -0500 ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic Reviewed-on: http://review.coreboot.org/44 The assumption that the devices are ordered in the tree seem to hold in this case (although it is not ensured) and therefore at least with the ASRock E350M1 no (visible) change is experienced as the children are all of type `DEVICE_PATH_PCI`. Change-Id: Iaa2fa13305dbe924965d27680cd02fe30c2f58a5 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/2562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-11AMD fam10: Link southbridge/amd/rs780/early_setup.cArthur Heymans
Removes rs780_before_pci_init() since it was a no-op anyway. Removes get_nb_rev() since this function is provided via a macro in the header. This Makes a lot of function non-static since the header has prototypes for these. Change-Id: I8933516771d959583bbd59a5c1beee3e30a7004f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-11-30amd/{hudson,stoneyridge}: fix out of bounds readRichard Spiegel
southbridge/amd/pi/hudson/imc.c procedure enable_imc_thermal_zone was identified by coverity as having out of bounds access. Copies of the procedure are present in southbridge/amd/agesa/hudson/imc.c and in soc/amd/stoneyridge/imc.c. Fix the procedure in all 3 files. Fixes coverity CID 1260807: Out-of-bounds read. BUG=b:69835834 TEST=Build and platform boot to OS Change-Id: Ic16edc607358b9a688151735e6fcb3393d3bce80 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-28AMD platforms: Fix ASL comment that implies "\_SB" is southbridgeMartin Roth
Change-Id: I6ee86396a1c5aaee248a275b42da801cedace586 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-03southbridge: Remove trailing space in `dump_south()` outputPaul Menzel
Change-Id: I4df9f8ce1058a2bb219508d0c8d04e153d37131c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/5179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-31AMD boards: Fix function name (soft_reset) in messageJonathan Neuschäfer
Change-Id: Ia21a3e93712bd6b6780fe7308c6cf79c553f4e1b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-10-12sb/amd/sb700/lpc.c: Optimize code flow for less indentationArthur Heymans
This changes the code flow so less indentation has to be used. This also changes some lines to limit their length. Change-Id: I50ca99a759a276e9d49327c6ae6c69eeab2a8c90 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21234 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-27smbus: Fix a typo ("Set the device I'm talking too")Jonathan Neuschäfer
Change-Id: Ia14bbdfe973cec4b366879cd2ed5602b43754260 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-26AGESA: Move API interface under drivers/Kyösti Mälkki
New AGESA support files will be used for binaryPI platforms as well. Furthermore, some of those should move from split nb/ sb/ directories to soc/, so move support files for the API under drivers/. Change-Id: I549788091de91f61de8b9adc223d52ffb5732235 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26AGESA: Implement POSTCAR_STAGEKyösti Mälkki
Move all boards that have moved away from AGESA_LEGACY_WRAPPER or BINARYPI_LEGACY_WRAPPER to use POSTCAR_STAGE. We use POSTCAR_STAGE as a conditional in CAR teardown to tell our MTRR setup is prepared such that invalidation without writeback is a valid operation. Change-Id: I3f4e2170054bdb84c72d2f7c956f8d51a6d7f0ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26AGESA cimx: Move cb_types.h to vendorcodeKyösti Mälkki
This file mostly mimics Porting.h and should be removed. For now, move it and use it consistently with incorrect form as #include "cbtypes.h". Change-Id: Ifaee2694f9f33a4da6e780b03d41bdfab9e2813e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-20vboot: remove init_vbnv_cmos()Aaron Durbin
Instead of having each potential caller deal with the differences of cmos_init() and init_vbnv_cmos() when VBOOT is enabled put the correct logic within the callee, cmos_init(), for handling the vbnv in CMOS. The internal __cmos_init() routine returns when the CMOS area was cleared. BUG=b:63054105 Change-Id: Ia124bcd61d3ac03e899a4ecf3645fc4b7a558f03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21549 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-14device: acpi_name() should take a const struct deviceAaron Durbin
There's no reason to mutate the struct device when determining the ACPI name for a device. Adjust the function pointer signature and the respective implementations to use const struct device. Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-13AGESA buildsystem: Reduce include path exposureKyösti Mälkki
Remove AGESA_AUTOINCLUDES -list from coreboot proper CPPFLAGS. Couple individual directories are now manually added to complete builds. Change-Id: I2595b87641c70e34e49fedf11b42f4961b0842dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA CIMX: Remove empty set_pcie_(de)resetKyösti Mälkki
For boards with cimx/sb800, mainboards defined only empty stubs. Reset functionality is handled as BiosCallout. For amd/inagua, the defined function was actually initial GPIO programming. For cimx/sb700, function had prototypes but no callers. For cimx/sb900, everything was commented out already. Change-Id: I936feb4fc41d903078620c919a733bb9f39c3efb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA boards: Clean up some includesKyösti Mälkki
Change-Id: I84c70aa04ab556a3898d3525f7b9aab85812f61d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-10amdfw: Clean up makefiles a bit moreMartin Roth
- Get rid of CONFIG_ prefix from variables that don't come from Kconfig. - Remove 2nd set of variables that are duplicates of the first set. - Delete duplicate set of Prerequisites Change-Id: I194b4c790b3e35353d480d34b60507a00f10ef11 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21451 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-09sb/amd: Support CBMEM_TOP_BACKUPKyösti Mälkki
Change-Id: I8d2005e4f2aa5a3b46e30f52556ee66aeb3d10cc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-06AGESA f15tn f16kb: Fix ACPI S3 resume for FCHKyösti Mälkki
This recovers FCH configuration on S3 resume path. Appearst to work, but other defects of HAVE_ACPI_RESUME must be fixed also before S3 support is re-enabled. Change-Id: I8d07d2e9dc161b67d854fcc8ec1da1f36900f989 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06ACPI S3: Remove conflicting local acpi_get_sleep_type()Kyösti Mälkki
We now require EARLY_CBMEM_INIT and romstage_handoff to support HAVE_ACPI_RESUME. Thus acpi_handoff_wakeup() would never call an externally defined acpi_get_sleep_type(). Name _sleep_type() was also inapproriate here, as it referred to hardware-dependent SLP_TYP field of PM1CNT but still returned ACPI_Sx value instead. Change-Id: I8dc130f1e86dd7e96922d546f0ae9713188336cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-08-28AGESA f15: Remove f10 referencesKyösti Mälkki
Vendorcode for f15 also has f10 support, so AMD_AGESA_FAMILY_10 was never selected. Change-Id: I9a026c36ace88f1110a52d7e24d3e6ab36508932 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-25amd/XX/hudson: Remove #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)Kyösti Mälkki
Remove the unnecessary #if from around the #include "fchec.h". Turn #if statements into if(). Change-Id: Ia0582b3ce24c55dd439dfadb727507240accd9d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-25amd/pi/hudson: Fix FCH ECMartin Roth
Move the fchec.h files, which do not seem mainboard specific, out of the mainboard directories into the southbridge/soc directories. Change-Id: Idd271c6ab618aa4badf81c702212e7de35317021 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-25amd/pi/hudson: Move oem_fan_control()Martin Roth
It was not intentional to change oem_fan_control() to non-static with commit 23e5ba9 binarypi mainboards: Clean up IS_ENABLED fan control Every platform except bettong had its own static version of oem_fan_control, so remove the definition of oem_fan_control from imc.h, and move it out of imc.c into bettong's BiosCallOuts.c. Change-Id: Ie95ac1fd3a57259bb35796903aa8753ef0e70d70 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21189 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-24amd/pi/hudson: Clean up makefile.incMarc Jones
Sort makefile.inc into rom, ram, ver, smm stages and alphabetize. Change-Id: Ic8c6ca2b57527fcc96c135cc801a098201bf0465 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24amd/pi/hudson: Convert 48Mhz en to read/write32Marshall Dawson
Change-Id: I91e09757e5eea1eaf9b76921ad032ad2b79c14c5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-23sb/amd/amd8111: Define ACPI sleep statesKyösti Mälkki
Note that against the specs, these definitions repeat the sleep type also in the reserved fields 3 and 4. For consistency, don't fix it here now. Entry for \_S3 is now masked off if HAVE_ACPI_RESUME=n. Change-Id: Icdc4c81d07fe7a99d5b0f8fa23e9443f58a40ab9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-23AGESA binaryPI: Consolidate and fix sleep statesKyösti Mälkki
SSFG was meant to be used as a mask to enable sleep states _S1 thru _S4. However as a logical instead of bitwise 'and' operation was used, all the states were enabled if only one was marked available. State _S3 is now set conditionally if HAVE_ACPI_RESUME=y. For pi/hudson this had been fixed already preprocessor. Note that all boards had SSFG == 0x0D that previously enabled ACPI S3 sleep state even when it was not available. States _S1 and _S2 still appear enabled in ASL/AML but may not actually work. TEST: 'cat /sys/power/state' and notice choice 'mem' was removed from the list of available sleep states. Change-Id: I27d616871c1771f0c87d8fba23d4ce1569607765 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-16AGESA: Cleanup ACPI S3 supportKyösti Mälkki
Due to low-memory corruptions S3 support has now been (at least temporarily) removed from AGESA platfroms. Should we bring it back one day, CAR teardown on S3 path will happen with an empty stack so ugly backup/recovery of the stack will no longer be used. If S3 feature is brought back, resume path code for FCH will also see partial rewrite and agesawrapper.c file will not be part of that. Change-Id: Ib38c04d0e74f600e0b719940d5e2530f4c726cfd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-07usbdebug: Refactor early enableKyösti Mälkki
Always sanity check for EHCI class device and move PCI function power enablement up. Change-Id: I1eebe813fbb420738af2d572178213fc660f392a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-07usbdebug: Consolidate EHCI_BAR setupKyösti Mälkki
There is assumption of static EHCI_BAR_INDEX, try to clean it up by bringing BAR programming at one spot. Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-04southbridge/pi/hudson: Fix GPIO bank1 control definitionMarshall Dawson
Change-Id: I3ef3ea3ea22faa0152d99923da2e57517ab3d0be Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-02AGESA: Introduce AGESA_LEGACY_WRAPPER and its counterpartKyösti Mälkki
We define AGESA_LEGACY_WRAPPER a method of calling AGESA via functions in agesawrapper.c file. The approach implemented there makes it very inconvenient to do board-specific customisation or present common platform-specific features. Seems like it also causes assertion errors on AGESA side. The flag is applied here to all boards and then individually removed one at a time, as things get tested. New method is not to call AGESA internal functions directly, but via the dispatcher. AGESA call parameters are routed to hooks in both platform and board -directories, to allow for easy capture or modification as needed. For each AGESA dispatcher call made, eventlog entries are replayed to the console log. Also relocations of AGESA heap that took place are recorded. New method is expected to be compatible with binaryPI. Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-18sb/amd/cs5536: Remove includes of C filesMartin Roth
The romstage for CS5536 platforms were including early_smbus.c and early_setup.c. Build these into romstage from the makefile, and remove the #includes. Add a Kconfig option for platforms that do not use the early smbus code. Change-Id: I2e6a9cd859292b4dd4720b547d1ff0bbb6c319cf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-17AGESA: Add guard for acpi_get_sleep_type()Kyösti Mälkki
With EARLY_CBMEM_INIT, this is defined from ACPI layer instead for ENV_RAMSTAGE. Change-Id: Ia9c1be4d3acaa0fa8827350558e6578c39b71602 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12binaryPI: Drop non-soc stoneyridge treesKyösti Mälkki
These sources are no longer part of build-tests and transition to soc/ appears to be completed. Change-Id: I9bc2212f44d79c795e5b8f6d62b6ee3c42de779a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-30southbridge/amd: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: I8fabb7331435eb518a5c95cb29c4ff5ca98560d2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-06-27vendorcode/amd: Unify Porting.h across all targetsStefan Reinauer
This requires to also unify the calling convention for AGESA functions from AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr) to AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr) On systems running 32bit x86 code this will not make a difference as UINTN is uintptr_t which is 32bit on these machines. Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-22sb/amd/rs780/gfx.c: Add brackets around macroElyes HAOUAS
Code checked manually Change-Id: I5a9596328c028d570303e9390c0133b19b97d683 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-13Consolidate reset API, add generic reset_prepare mechanismJulius Werner
There are many good reasons why we may want to run some sort of generic callback before we're executing a reset. Unfortunateley, that is really hard right now: code that wants to reset simply calls the hard_reset() function (or one of its ill-differentiated cousins) which is directly implemented by a myriad of different mainboards, northbridges, SoCs, etc. More recent x86 SoCs have tried to solve the problem in their own little corner of soc/intel/common, but it's really something that would benefit all of coreboot. This patch expands the concept onto all boards: hard_reset() and friends get implemented in a generic location where they can run hooks before calling the platform-specific implementation that is now called do_hard_reset(). The existing Intel reset_prepare() gets generalized as soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now easily be added later if necessary). We will also use this central point to ensure all platforms flush their cache before reset, which is generally useful for all cases where we're trying to persist information in RAM across reboots (like the new persistent CBMEM console does). Also remove cpu_reset() completely since it's not used anywhere and doesn't seem very useful compared to the others. Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19789 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-07spi: Remove unused/unnecessary spi_init function definitionsFurquan Shaikh
Remove spi_init definitions which: 1. Do nothing 2. Set static global variables to 0 Change-Id: If4c0cdbe2271fc7561becd87ad3b96bd45e77430 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20039 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-27CBMEM: Clarify CBMEM_TOP_BACKUP function usageKyösti Mälkki
The deprecated LATE_CBMEM_INIT function is renamed: set_top_of_ram -> set_late_cbmem_top Obscure term top_of_ram is replaced: backup_top_of_ram -> backup_top_of_low_cacheable get_top_of_ram -> restore_top_of_low_cacheable New function that always resolves to CBMEM top boundary, with or without SMM, is named restore_cbmem_top(). Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-24southbridge/amd: Move spi driver to use spi_bus_mapFurquan Shaikh
This is in preparation to get rid of the strong spi_setup_slave implemented by different platforms. BUG=b:38430839 Change-Id: I2a789cff40fb0e6bd6d84565531d847afb3f8bed Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-18AGESA: Fix UMA calculationsKyösti Mälkki
Vendorcode decides already in AMD_INIT_POST the exact location of UMA memory. To meet alignment requirements, it will extend uma_memory_size. We cannot calculate base from size and TOP_MEM1, but need to calculate size from base and TOP_MEM1 instead. Also allows selection of UmaMode==UMA_SPECIFIED to manually set amount of memory reserved for framebuffer. Change-Id: I2514c70a331c7fbf0056f22bf64f19c9374754c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-05-11amd/pi: Add AMD fam16h TPM ACPI path supportPhilipp Deppenwiese
Change-Id: I5322d731a0dc655f2da14b87fa6cbc1e54b5abd5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/18522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-05drivers/spi: Re-factor spi_crop_chunkFurquan Shaikh
spi_crop_chunk is a property of the SPI controller since it depends upon the maximum transfer size that is supported by the controller. Also, it is possible to implement this within spi-generic layer by obtaining following parameters from the controller: 1. max_xfer_size: Maximum transfer size supported by the controller (Size of 0 indicates invalid size, and unlimited transfer size is indicated by UINT32_MAX.) 2. deduct_cmd_len: Whether cmd_len needs to be deducted from the max_xfer_size to determine max data size that can be transferred. (This is used by the amd boards.) Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19386 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: coreboot org <coreboot.org@gmail.com>
2017-05-02amd/pi/hudson: Add config option for ACPI baseMarc Jones
Add a configuration option to assign the binaryPI base address for the ACPI registers. The binaryPI's assignment is determine at build time and no run-time configuration is allowed. Change-Id: Ida17022abfa6faceb0653c2cb87aacce4facef09 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19485 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-27amd/pi/hudson: Add VBNV cmos reset optionMarc Jones
If the mainboard supports VBNV, call init_vbnv_cmos() instead of the normal init_cmos(). The VBNV version does some VBNV pre and post setup around the normal init_cmos(). Change-Id: I34b02409019b945cd68c830e006e99338643f29c Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19399 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-27Revert "amd/pi/hudson: Move ACPI IO registers"Kyösti Mälkki
This reverts commit e7394ca90366d35ac52416c21052a3ceb459dc81. Configuration register for ACPI PM base address is initially configured inside the PI blob. Therefore, the value of HUDSON_ACPI_IO_BASE needs to be the same as DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS used in the build of binaryPI blob. Change-Id: I36700e49e21cc675e8e22b06efffb40e9c1e4236 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19454 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins)
2017-04-26amd/pi/hudson: Add TPM decode to SPI functionMarc Jones
Add a function to send the TPM decode to the SPI interface. Enables use of SPI TPMs on Hudson mainboards. Change-Id: I0e85ed92163e38eca6a55456708ab322d6a90d4c Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19402 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-26amd/pi/hudson: Clean up whitespace in header filesMarshall Dawson
Change spaces to tabs and do general whitespace cleanup. Change-Id: I4a4ecd42f91c9c6015a4f065b7386b17523ac6d9 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19401 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-26amd/pi/hudson: Move ACPI IO registersMarc Jones
Move the ACPI IO registers from 0x800 to 0x600 to avoid the IO space required by the Google EC, also at 0x800. This shouldn't have any conflicts on other AMD systems. Change-Id: Iac7388c15e899277fd506fb37965164488358335 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19171 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-26amd/pi/hudson: Add LPC IO decode enable functionMarc Jones
Add a function to enable LPC IO decode AKA WideIO. This can enable up to 3 regions, which may be 512 or 16 bytes wide. Change-Id: I2bed3a99180188101e00b4431d634227e488cbda Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19160 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-25amd/pi/hudson: Add GPIO get functionMarc Jones
Add a basic GPIO get function. Note that GPIO set, ACPI/GPE, and other features should come in future commits. Future changes to be modeled on the other soc/ gpio functions. Change-Id: I8f681865715ab947b525320a6f9fc63af1334b59 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19159 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-17[nb|sb]/amd/[amdfam10|sb700]: Add LPC bridge ACPI names for NB/SBTimothy Pearson
Adds the necessary plumbing for acpi_device_path() to find the LPC bridge on the AMD Family10h/15h northbridges and SB700 southbridge. This is necessary for TPM support since the acpi path to the LPC bridge doesn't match the built-in default in tpm.c This is a port of GIT hash d8a2c1fb by Tobias Diedrich. BUG=https://ticket.coreboot.org/issues/102 Change-Id: I1c514e335e194b2864599e5419cfaee830b94e38 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/19282 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-17sb/amd/pi/hudson: Spell verb in comment with a spacePaul Menzel
Change-Id: I7d0d8e2a20d15cbed30e98cf4468e9fb5dd0f1ad Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/19292 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-15sb/amd/sb700: Disable LPC ROM mapping when SPI Flash is usedTimothy Pearson
Do not map LPC ROM into the system memory space when SPI Flash is configured instead of an LPC ROM. This resolves a long-standing hard boot hang issue on the ASUS KGPE-D16 and related systems; in a nutshell, the incorrectly mapped LPC ROM overrode low memory required by ramstage, causing decompressed ramstage layout-dependent vectoring to romstage code and subsequent execution of random sections of romstage. Sometimes these random sections of romstage reconfigured the hardware in such a way that it could not access SPI Flash on the next boot attempt. Change-Id: I115e5d834f0ca99c2d9dbb5b9b5badbea1d98574 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/19280 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Daniel Kulesz <daniel.ina1@googlemail.com>
2017-04-14amd/pi/hudson: Add SERIRQ setupMarc Jones
Enable SERIRQ in quiet or continuous mode based on Kconfig. Defaults to quite mode. Change-Id: Ib40a84719fcc3a5d6b3000c3c0412f1bcf629609 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19234 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-14amd/pi/hudson: Add hudson PM register definesMarc Jones
Clean up hudson PM register accesses with some register defines. Change-Id: I5ccf27a2463350baec53b7c79fe0fd4ec6c31306 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19233 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-06northbridge/amd/stoney: Add FT4 packageMarshall Dawson
Add package options to the CPU Kconfig that may be selected by the mainboard's Kconfig file. Stoney Ridge is available in FP4 and FT4 packages and each requires a unique binaryPI image. Default to the correct blob used by the northbridge by looking at the CPU's package. Also modify Gardenia to select the right package. See the Infrastructure Roadmap for FP4 (#53555) and FT4 (#55349) for additional details for the packages. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 7b8ed7b732b7cf5503862c5edc6537d672109aec) Change-Id: I7bb15bc4c85c5b4d3d5a6c926c4bc346a282ef27 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18989 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-03cimx/sb800: Log southbridge call-sitesKyösti Mälkki
Logging makes it easier to track order of events as these call-sites are scattered on various files. Change-Id: I428547051fd8bf487e91415dc72ee03dba13029e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28amd/pi/hudson: Add fanless SMU firmware to buildMarshall Dawson
Use the new parameters in amdfwtool to include the additional SMU firmware into amdfw.rom. Change-Id: Ib44860780c8d5fb00c47f775a2a83b82ff3e1821 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19002 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28amd/pi/hudson: Reduce amdfw space requirementMarshall Dawson
Change the current implementation so that multiple PSP directory structures are not included, saving 448 KB. AMD created a mechanism so that multiple generations of APUs, in identical packages, may be supportable in one BIOS image. The PSP identifies the correct directory table by checking one of two pointers in the Embedded Firmware structure. Coreboot doesn't implement this capability, however it has been constructing amdfw.rom with two identical directory tables and two copies of each PSP blob. Tested on Bettong (Merlin Falcon / Carrizo) and Jadeite (Stoney). Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 11dfc3f621344db66d92b61d72927128ea48685f) Change-Id: I139f3bfdb319af803fef64e7bd848e95945f41aa Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18990 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28amd/pi/hudson: Add alternate method for including amdfwMarshall Dawson
For systems using Chrome OS, place the amdfw outside of cbfs control. The firmware must go to a fixed position at an offset of 0x20000 into the flash device. Potentially improve by adding a warning or error message for the condition when sizeof(amdfw) + sizeof(cbfs and metadata) > sizeof(flash). Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 2d9d631b39d7850576438a5b0979936bd33893e1) Change-Id: I38029bc03e5db260424cca293b1a7bceea4d0d75 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18435 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-08AGESA: Move heap allocator declarationsKyösti Mälkki
Definitions are not part of ACPI S3 feature, nor do they require any AGESA headers so move them to a better location. Change-Id: I9269e9d65463463d9b8280936cf90ef76711ed4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18616 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-07amd/pi/hudson: Move APIC enable to CPU fileMarshall Dawson
Relocate the enabling of the LAPIC out of the southbridge source and surround it with a check for CONFIG_UDELAY_LAPIC (typical for AMD systems). The LAPIC is now enabled for all cores; not only the BSP, and not only when the UART is used. This solves the problem of APs not having their APICs enabled when the timer is expected to be functional, e.g. verstage often uses do_printk_va_list() instead of do_printk() which exits early for APs when CONFIG_SQUELCH_EARLY_SMP=y. The changes were tested with two Gardenia builds, one using verstage and another with CONFIG_SQUELCH_EARLY_SMP=n. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 93ffc311165f19d4192a5489051fa4264cd8e0ad) Change-Id: Ieaecc0bf921ee0d2691a8082f2431ea4d0c33749 Signed-off-by: Marc Jones <marcj303@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18436 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07amd/pi/hudson/acpi: Only declare S3 if it is supportedMarc Jones
Only declare S3 support in ACPI if CONFIG_HAVE_ACPI_RESUME is set. Change-Id: I6f8f62a92478f3db5de6feaa9822baad3f8e147e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18493 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07amd/pi/hudson: Add early SPI setupMarshall Dawson
Add some generic functions that can configure the SPI interface to have faster performance. Given that the hudson files are used across many generations of FCHs, make sure to refer to the appropriate BKDG or RRG before using the functions. Notable differences: * Hudson 1 defines read mode in CNTRL0 differently than later gens * Hudson 1 supports setting NormSpeed in Cntr1 but Hudson3 allows setting FastSpeed as well * Kabini, Mullins, Carrizo and Stoney Ridge contain a "new" SPI100 controller Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 1922d6f424dcf1f42e2f21fb7c6d53d7bcc247d0) Change-Id: Id12440e67bc575dbe4b980ef1da931d7bfae188d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18442 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07amd/pi/hudson: Add SPI definitions to headerMarshall Dawson
Add defines that will be used later for setting the fastest settings in the SPI controller. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 0d2c28b8156dcc1f3dc925b3c3ba15b6b07f202c) Change-Id: I660cc9ed6910c33042321c80453c7f74912455d9 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18441 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07amd/pi/hudson: Consolidate BITn definitionsMarshall Dawson
Remove unused definitions from a .c file and use the BIT(n) macro found in types.h instead. Convert existing definitions to BIT(n). Orignial-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit f403d12b49985ee9d9b339a6659b60ef1560519c) Change-Id: I24105bf75263236dbdbc2666f03033069d1d36d2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18440 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07AGESA: Remove redundant and invalid IRQ routingKyösti Mälkki
The size of the array did not match that of the actual allocation. Furthermore, the tables are written as part of set_pci_irqs() in hudson/pci.c. Also the removed code was never reached runtime, as it is only executed on ACPI S3 resume path that is currently disabled. Change-Id: If1c47d53a7656bdff40d93fc132c8c057184ae46 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18587 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-22southbridge/amd: Add LPC bridge acpi path for Family14 and SB800Tobias Diedrich
Adds the necessary plumbing for acpi_device_path() to find the LPC bridge on the AMD Family14 northbridge with an SB800 southbridge. This is necessary for TPM support since the acpi path to the LPC bridge (_SB.PCI0.ISAB) doesn't match the built-in default in tpm.c (_SB.PCI0.LPCB). Change-Id: I1ba5865d3531d8a4f41399802d58aacdf95fc604 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/18402 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-01-10amd/hudson/agesa: Fix position of hudson_fwmRicardo Ribalda Delgado
AMDFWTOOL calculates the location of the amdfw based on the CONFIG_ROM_SIZE. If HUDSON_FWM_POSITION does not match that location the resulting rom does not boot. This patch forces the position of HUDSON_FWM_POSITION to be the position calculated by amdfwrom. Tested on a Bettong derivative with a 16MiB flash. Change-Id: I3ce69f77174327c18ff97e551c0665c9f633991e Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/17934 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-01-10amd/hudson/pi: Fix position of hudson_fwmRicardo Ribalda Delgado
AMDFWTOOL calculates the location of the amdfw based on the CONFIG_ROM_SIZE. If HUDSON_FWM_POSITION does not match that location the resulting rom does not boot. This patch forces the position of HUDSON_FWM_POSITION to be the position calculated by amdfwrom. Tested on a Bettong derivative with a 16MiB flash. Change-Id: Id2ee96ee076293d48ade84fd6e976ca994dcf491 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/17925 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-01-05src/amd: Add common definition of AMD ACPI MMIO addressTimothy Pearson
The bare ACPI MMIO address 0xFED80000 was used in multiple AMD mainboard files as well as the SB800 native code. Reduce duplication by using a centrally defined value for all AMD ACPI MMIO access. Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18032 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-04amdfam10: Perform major include ".c" cleanupDamien Zammit
Previously, all romstages for this northbridge family would compile via 1 single C file with everything included into the romstage.c file (!) This patch separates the build into separate .o modules and links them accordingly. Currently compiles and links all fam10 roms without breaking other roms. Both DDR2 and DDR3 have been completed TESTED on REACTS: passes all boot tests for 2 boards ASUS KGPE-D16 ASUS KFSN4-DRE Some extra changes were required to make it compile otherwise there were unused functions in included "c" files. This is because I needed to exchange CIMX for the native southbridge routines. See in particular: advansus/a785e-i asus/m5a88-v avalue/eax-785e A followup patch may be required to fix the above boards. See FIXME, XXX tags Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/17625 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2016-12-23spi: Get rid of SPI_ATOMIC_SEQUENCINGFurquan Shaikh
SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with the ability to perform tx and rx of flash command and response at the same time. Instead of introducing this notion at SPI flash driver layer, clean up the interface to SPI used by flash. Flash uses a command-response kind of communication. Thus, even though SPI is duplex, flash command needs to be sent out on SPI bus and then flash response should be received on the bus. Some specialized x86 flash controllers are capable of handling command and response in a single transaction. In order to support all the varied cases: 1. Add spi_xfer_vector that takes as input a vector of SPI operations and calls back into SPI controller driver to process these operations. 2. In order to accomodate flash command-response model, use two vectors while calling into spi_xfer_vector -- one with dout set to non-NULL(command) and other with din set to non-NULL(response). 3. For specialized SPI flash controllers combine two successive vectors if the transactions look like a command-response pair. 4. Provide helper functions for common cases like supporting only 2 vectors at a time, supporting n vectors at a time, default vector operation to cycle through all SPI op vectors one by one. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17681 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19pcengines/apu2: add board supportPiotr Król
Initial work based on db-ft3b-ls and code released by Eltan. Board boots with some limitation. Now the AGESA binary is harcoded and board specific until it's fixed by the SoC vendor. memtest86+ from external repo skips looking for SPD on SMBus, which when performed cause memtest86+ to hang. Still didn't tried whole test suit. SeaBIOS 1.9.3 have some problems with USB which lead to no booting in some cases. Full log: https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872 SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios) works fine. Those changes are planned for upstream. Information about obtaining and booting Voyage Linux: https://github.com/pcengines/apu2-documentation#building-firmware-using-apu2-image-builder Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/14138 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-12-06PCI ops: Remove conflicting duplicate declarationsKyösti Mälkki
The code originates from times before __SIMPLE_DEVICE__ was introduced. To keep behaviour unchanged, use explicit PCI IO operations here. Change-Id: I44851633115f9aee4c308fd3711571a4b14c5f2f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17720 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05mainboard & southbridge: Clear files that are just headersMartin Roth
These headers & comments indicating a lack of functionality don't help anything. We discourage copyrights and licenses on empty files, so just clear these. Change-Id: Id2ab060a2726cac6ab047d49a6e6b153f52ffe6d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17657 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-05spi: Define and use spi_ctrlr structureFurquan Shaikh
1. Define a new structure spi_ctrlr that allows platforms to define callbacks for spi operations (claim bus, release bus, transfer). 2. Add a new member (pointer to spi_ctrlr structure) in spi_slave structure which will be initialized by call to spi_setup_slave. 3. Define spi_claim_bus, spi_release_bus and spi_xfer in spi-generic.c which will make appropriate calls to ctrlr functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Icb2326e3aab1e8f4bef53f553f82b3836358c55e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17684 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Pass pointer to spi_slave structure in spi_setup_slaveFurquan Shaikh
For spi_setup_slave, instead of making the platform driver return a pointer to spi_slave structure, pass in a structure pointer that can be filled in by the driver as required. This removes the need for platform drivers to maintain a slave structure in data/CAR section. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia15a4f88ef4dcfdf616bb1c22261e7cb642a7573 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17683 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Fix parameter types for spi functionsFurquan Shaikh
1. Use size_t instead of unsigned int for bytes_out and bytes_in. 2. Use const attribute for spi_slave structure passed into xfer, claim bus and release bus functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ie70b3520b51c42d750f907892545510c6058f85a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17682 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AMD binaryPI: Use explicit PCI IO config access in bootblockKyösti Mälkki
This allows us to set MMCONF_SUPPORT_DEFAULT since we enable MMCONF early in romstage. Change-Id: I380cf483bfe4e2d64969110ae6d5d04c3ced2418 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17532 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AGESA: Use explicit PCI IO config access in bootblockKyösti Mälkki
This allows us to set MMCONF_SUPPORT_DEFAULT since we enable MMCONF early in romstage. Change-Id: I994bb257db96300c2eb8872be6fae2a92bbabab4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17531 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-23AGESA binaryPI: Fix PCI ID namespaceKyösti Mälkki
The defines of device IDs reflects the vendor namespace the ID has been allocated from. Change-Id: Id98f45d5984752a9e8c0484d4cb94e93e55b12f6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17510 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-22spi: Clean up SPI flash driver interfaceFurquan Shaikh
RW flag was added to spi_slave structure to get around a requirement on some AMD flash controllers that need to group together all spi volatile operations (write/erase). This rw flag is not a property or attribute of the SPI slave or controller. Thus, instead of saving it in spi_slave structure, clean up the SPI flash driver interface. This allows chipsets/mainboards (that require volatile operations to be grouped) to indicate beginning and end of such grouped operations. New user APIs are added to allow users to perform probe, read, write, erase, volatile group begin and end operations. Callbacks defined in spi_flash structure are expected to be used only by the SPI flash driver. Any chipset that requires grouping of volatile operations can select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and define callbacks for chipset_volatile_group_{begin,end}. spi_claim_bus/spi_release_bus calls have been removed from the SPI flash chip drivers which end up calling do_spi_flash_cmd since it already has required calls for claiming and releasing SPI bus before performing a read/write operation. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-21AMD binaryPI: Drop commented code with bad PCI IDsKyösti Mälkki
There is mismatch of VENDOR_ID_AMD with DEVICE_ID_ATI, also the device IDs have not been defined. Change-Id: I3076cb08e3181e7f86de38deb18f1661f037bc38 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17508 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-21AGESA: Drop commented code with bad PCI IDsKyösti Mälkki
There is mismatch of VENDOR_ID_AMD with DEVICE_ID_ATI, also the device IDs have not been defined. Change-Id: I0d85893169fe877e384746931605f563c50308b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17509 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-21AMD sb700: Fix PCI ID errorKyösti Mälkki
Broken since March 2010, looking for incorrect PCI VENDOR. Change-Id: I1960aa168e59364ad962f00c81b67b8bdc5773ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17514 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-21AMD sb600: Fix PCI ID errorKyösti Mälkki
Broken since February 2008, looking for incorrect PCI VENDOR. Change-Id: I6935683a8a7428ca9b2e90bcc0a090c3865ffd33 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17513 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10southbridge/amd: Remove debug echo when building PIMartin Roth
If this information is needed, use make V=1. That will print the actual command, not a command that needs to be updated with every addition if it's going to stay in sync. Change-Id: I64d33d93c7fad3359d8ef78657bdb86d1fb4d4a1 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17328 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10southbridge/amd: update for amdfwtool size on command lineMartin Roth
amdfwtool was getting the ROM size as a #define when it was built. It has been updated to pass it in as a command line parameter, so now it can be built just once for abuild as a shared tool. Update the calls to amdfwtool to pass the ROM size. All platforms using amdfwtool had the output verified using a binary compare. This reverts commit 0529236ed22f1a28d29f2054674004c4f7a056e7 (Makefile.inc: Don't share amdfwtool between platforms) Change-Id: I188b34e08249f2d00bd48957ced750b21f1ec348 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17327 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-07southbridge/amd: Update Kconfig and makefiles for 00670F00Marc Jones
Add Stoney specific code subtree and fix Makefles and Kconfig files. Author: Charles Marslett <charles@scarlettechnologies.com> Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit c3a469d11e4676b3b63d11a30955113291d00ec8) Change-Id: Ic4d97a3745f7fc5a637ae6da17a9009b9757136e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17217 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07amd/pi/hudson: Move audio to northbridgeMarshall Dawson
Carrizo (00660F01), Merlin Falcon (00660F01), and Stoney Ridge (00670F00) locate the HD audio controller on the northbridge root complex at 9.2 instead of the FCH. This duplicates the existing ASL into the northbridge directories and reports the correct address. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit f68206c2b42c90076efd968a99f4d3a49e403438) Change-Id: I6d42bb40ad58c7f35e8c88ff27ebd327d656c021 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17216 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>