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path: root/src/southbridge/amd/sr5650
AgeCommit message (Expand)Author
2018-07-09src/southbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
2018-06-14src: Use of device_t is deprecatedElyes HAOUAS
2018-06-04sb/amd/sr5650: Fix invalid function declarationsKyösti Mälkki
2018-05-23sb/amd/sr5650: Get rid of device_tKyösti Mälkki
2018-05-08src/southbridge: Add required space before the open parenthesisElyes HAOUAS
2017-10-31AMD boards: Fix function name (soft_reset) in messageJonathan Neuschäfer
2017-08-28AGESA f15: Remove f10 referencesKyösti Mälkki
2017-06-30southbridge/amd: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
2016-09-15southbridge/amd/sr5650/sr5650.c: Update acpi_fill_ivrsMartin Roth
2016-09-15amd/sr5650: Update add_ivrs_device_entriesMartin Roth
2016-09-07include/arch/acpi.h: change IVRS efr field to iommu_feature_infoMartin Roth
2016-08-31src/southbridge: Code formatingElyes HAOUAS
2016-07-31src/southbridge: Capitalize CPU, RAM and ROMElyes HAOUAS
2016-01-18header files: Fix guard name comments to match guard namesMartin Roth
2016-01-04sb/amd/sr5650: Correctly locate CPU MMCONFIG resourceTimothy Pearson
2015-12-18southbridge/amd/sr5650: Add MCFG ACPI table supportTimothy Pearson
2015-12-13amd/[nb/fam10|sb/sr5650]: Minor cosmetic changesTimothy Pearson
2015-12-08sb/amd/sr5650: Allow resource allocator to assign bus numbersTimothy Pearson
2015-11-26southbridge/amd/sr5650: Use correct PCI configuration block offsetTimothy Pearson
2015-11-23southbridge/amd/sr5650: Hide clock configuration device after setup is completeTimothy Pearson
2015-11-23southbridge/amd/sr5650: Add IOMMU supportTimothy Pearson
2015-11-15src/southbridge/amd/sr5650: Always configure lane director on startupTimothy Pearson
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-26southbridge/amd/sr5650: Add AMD Family 15h CPU supportTimothy Pearson
2015-10-24southbridge/amd/sr5650: Fix hardcoded printk() function names in pcie.cTimothy Pearson
2015-10-24southbridge/amd/sr5650: Fix boot failure on ASUS KGPE-D16Timothy Pearson
2015-10-24southbridge/amd/sr5650: Add optional delay after link trainingTimothy Pearson
2015-10-23southbridge/amd/sr5650: Fix GPP3a link training in higher width modesTimothy Pearson
2015-10-16southbridge/amd/sr5650: Remove unnecessary register configurationTimothy Pearson
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-04-27kbuild: automatically include southbridgesStefan Reinauer
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
2014-12-17southbridge/amd amd81XX, cs553X & sr5650 spelling fixesMartin Roth
2014-12-09southbridge/amd/sr5650/sr5650.c: Fix bitwise logic and mask in loopEdward O'Callaghan
2014-07-29Uniformly spell frequency unit symbol as HzElyes HAOUAS
2013-04-11AMD RS780, SR5650: PcieTrainPort: Fix typo *i*gnoring in commentPaul Menzel
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2012-11-27Get rid of drivers classPatrick Georgi
2012-11-20Unify use of bool config variablesStefan Reinauer
2012-08-22Auto-declare chip_operationsKyösti Mälkki
2012-05-08Some more #if cleanupPatrick Georgi
2012-02-20Fixes Fam10/SR5650 cpu not recognized message.Dave Frodin
2011-11-01remove trailing whitespaceStefan Reinauer
2011-10-30Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c.Stefan Reinauer
2011-07-22Update AMD SR5650 and SB700efdesign98
2011-03-27Add AMD SR56x0 support.Zheng Bao
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