coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-10-30	{cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros	Elyes HAOUAS
2018-10-18	cpu/amd: Use common AMD's MSR	Elyes HAOUAS
2018-07-09	src/southbridge: Use "foo bar" instead of "foo bar"	Elyes HAOUAS
2018-06-14	src: Get rid of unneeded whitespace	Elyes HAOUAS
2018-06-04	sb/amd/sr5650: Fix invalid function declarations	Kyösti Mälkki
2018-05-23	sb/amd/sr5650: Get rid of device_t	Kyösti Mälkki
2016-09-15	southbridge/amd/sr5650/sr5650.c: Update acpi_fill_ivrs	Martin Roth
2016-09-15	amd/sr5650: Update add_ivrs_device_entries	Martin Roth
2016-09-07	include/arch/acpi.h: change IVRS efr field to iommu_feature_info	Martin Roth
2016-08-31	src/southbridge: Code formating	Elyes HAOUAS
2016-07-31	src/southbridge: Capitalize CPU, RAM and ROM	Elyes HAOUAS
2016-01-04	sb/amd/sr5650: Correctly locate CPU MMCONFIG resource	Timothy Pearson
2015-12-18	southbridge/amd/sr5650: Add MCFG ACPI table support	Timothy Pearson
2015-11-23	southbridge/amd/sr5650: Add IOMMU support	Timothy Pearson
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-24	southbridge/amd/sr5650: Fix boot failure on ASUS KGPE-D16	Timothy Pearson
2015-10-24	southbridge/amd/sr5650: Add optional delay after link training	Timothy Pearson
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-12-17	southbridge/amd amd81XX, cs553X & sr5650 spelling fixes	Martin Roth
2014-12-09	southbridge/amd/sr5650/sr5650.c: Fix bitwise logic and mask in loop	Edward O'Callaghan
2013-04-11	AMD RS780, SR5650: PcieTrainPort: Fix typo ignoring in comment	Paul Menzel
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2011-11-01	remove trailing whitespace	Stefan Reinauer
2011-07-22	Update AMD SR5650 and SB700	efdesign98
2011-03-27	Add AMD SR56x0 support.	Zheng Bao