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path: root/src/southbridge/amd/sr5650/pcie.c
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2019-03-03device/pci_ops: Drop unused parameterKyösti Mälkki
Drop the bus parameter, we do not use it. It would still be possible to do per-bus selection by evaluating the bus number, but currently we do not have need for that either. Change-Id: I09e928b4677d9db2eee12730ba7b3fdd8837805c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06device: Use pcidev_on_root()Kyösti Mälkki
Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-04device: Replace ugly cases of dev_find_slot()Kyösti Mälkki
These few cases lacked a proper devfn parameter in the form of PCI_DEVFN(dev, fn). Change-Id: Iad0b214df12dee65360d07e887a960b0c73a3e4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-12-19southbridge: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Ia640131479d4221ccd84613033f28de3932b8bff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-23sb/amd/sr5650: Get rid of device_tKyösti Mälkki
Change-Id: If03864d5e32dfc4a2e5e11a96a4df62699ca4392 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08sb/amd/sr5650: Allow resource allocator to assign bus numbersTimothy Pearson
At some point in the past disconnected PCIe bridges were completely disabled to work around a hang on bridge probe. This hang was resolved at some point, and the disconnected PCIe bridges should be enabled to receive a bus number per the RPR. This resolves a slew of warnings in the Linux boot log regarding invalid bridge configurations for disconnected bridge devices. Change-Id: Ic26e2d62ec5ddb9f22275c2afec7d560326263c7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12673 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-23southbridge/amd/sr5650: Hide clock configuration device after setup is completeTimothy Pearson
Change-Id: I043f2eb0993660d0a9351867eca1e73e0b2c37f1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12045 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-15src/southbridge/amd/sr5650: Always configure lane director on startupTimothy Pearson
On the ASUS KGPE-D16 it was noted that the pin straps did not properly configure the lane director hardware, causing link training failure on NIC B. Forcing coreboot to always reconfigure the lane director on startup resolves this problem. Change-Id: I5b78cef84960e0f42cc3e0406a7031d12d21f3ad Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12014 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-24southbridge/amd/sr5650: Fix hardcoded printk() function names in pcie.cTimothy Pearson
Change-Id: Idf1db091f1d1e40ce2f248bc25d662cf9608b27e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12179 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-24southbridge/amd/sr5650: Fix boot failure on ASUS KGPE-D16Timothy Pearson
Change-Id: Ia13ba58118a826e830a4dc6e2378b76110fcabad Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11939 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-23southbridge/amd/sr5650: Fix GPP3a link training in higher width modesTimothy Pearson
Change-Id: I7503ae42eb8bc91411413ef2cc7e7a723df7091a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11990 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins)
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-12-17southbridge/amd amd81XX, cs553X & sr5650 spelling fixesMartin Roth
Trivial fixes, but the editor highlights them, and it's easy to go through a bunch of files while I'm otherwise idle. Change-Id: Ice5d8ce9408356c866a9a2ee5a03f704f55ddc2a Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7842 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2011-11-01remove trailing whitespaceStefan Reinauer
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-30Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c.Stefan Reinauer
Change-Id: I3ccb3860207e1b3ccac4313f7b537c434af5166f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/360 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-07-22Update AMD SR5650 and SB700efdesign98
This updates the code for the AMD SR5650 and SB700 southbridges. Among other things, it changes the romstage.c files by replacing a .C file include with a pair of .H file includes. The .C file is now added to the romstage in the SB700 or SR5650 Makefile.inc. file to the romstage and ramstage elements. This particular change affects all mainboards that use the SB700, and their changes are include herein. These mainboards are: Advansus a785e, AMD Mahogany, Mahogany-fam10, Tilapia-fam10, Asrock 939a785gmh, Asus m4a78-em, m4a785-m, Gigabyte ma785gm, Iei Kino-780am2-fam10 Jetway pa78vm5 Supermicro h8scm_fam10 The nuvoton/wpcm450 earlysetup interface is changed because the file is no longer included in the mainboard romstage.c files. Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/107 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-03-27Add AMD SR56x0 support.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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