coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-04	arch/io.h: Drop unnecessary include	Kyösti Mälkki
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2018-12-19	southbridge: Remove useless include <device/pci_ids.h>	Elyes HAOUAS
2017-04-15	sb/amd/sb700: Disable LPC ROM mapping when SPI Flash is used	Timothy Pearson
2016-08-31	amd/sb700/bootblock.c: Restore accidentally deleted code	Martin Roth
2016-08-31	src/southbridge: Code formating	Elyes HAOUAS
2016-08-26	sb/amd/sb700: Add option to increase SPI speed to 33MHz	Timothy Pearson
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-25	southbridge/amd/sb700: Set up uninitialized devices in early boot	Timothy Pearson
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-11-05	soutbridge/*/bootblock: Use pci_dev_t over device_t typedef	Edward O'Callaghan
2013-03-22	x86: Unify arch/io.h and arch/romcc_io.h	Stefan Reinauer
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-02-20	Force SB700 bootblock code to use I/O for PCI config cycles.	Dave Frodin
2011-03-28	SP5100's code is based on SB700. Change the legacy sb700 of sb7xx_51xx.	Zheng Bao
2010-12-14	Set the ROMSIZE as 4MB.	Zheng Bao
2010-12-10	Add TINY_BOOTBLOCK support for AMD SB700.	Uwe Hermann