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2017-06-30southbridge/amd: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: I8fabb7331435eb518a5c95cb29c4ff5ca98560d2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31src/southbridge: Capitalize CPU, RAM and ROMElyes HAOUAS
Change-Id: I01413b9f8b77ecdcb781340f04c2fe9e24810264 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15941 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
2015-12-18southbridge/amd/sr5650: Add MCFG ACPI table supportTimothy Pearson
As the southbridge largely controls the PCI[e] configuration space this patch moves the resource allocation from the northbridge to the southbridge when the extended configuration space region is enabled. Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12050 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-03-19southbridge/amd/rs780: Remove requirement for CF8/CFC config accessKyösti Mälkki
The AMD RS780 early initialization code originally used the CF8/CFC I/O method for PCI configuration space access. After the default configuration access method was changed to MMIO (http://review.coreboot.org/#q,aad07472), booting would hang at "PCI: pci_scan_bus for bus 01". Fix the problem by changing function rs780_nb_gfx_dev_table() so that it no longer borrows the BAR3 address needed for PCIe MMIO config usage. Change-Id: I8816b94c848e1b50f8c880e5867a96ca2a33a8a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8394 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-07-16Define global uma_memory variablesKyösti Mälkki
Use of the uma_memory_base and _size variables is very scattered. Implementation of setup_uma_memory() will appear in each northbridge. It should be possible to do this setup entirely in northbridge code and get rid of the globals in a follow-up. Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-08Clean up #ifsPatrick Georgi
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com>
2011-11-01remove trailing whitespaceStefan Reinauer
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-15AMD CPU and chipset fixes for compilation with gcc 4.6Stefan Reinauer
Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/266 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-09-14rs780: hide unused gfx ports and gpp portsKerry Sheh
Hide the unused gfx ports and gpp ports if they are not configured as hotplug. lspci -vvv will get more accurate information under Linux, tested on avalue/eax-785e. Change-Id: Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/206 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2010-11-24This patch solves crashes and BSODs that occur when booting Win7 withScott Duplichan
AMD RS780 uma graphics. Tested with frame buffer sizes 64m through 1GB by running dxdiag and Windows media player at 1600x1200 true color. Additional changes needed to boot Win7 on Mahogany_fam10 will follow. -- Enable and program the debug bar as required by the ATI graphics driver. First, make the debug bar writable and allow resource allocation code to program it. Once programmed, enable its operation. -- Disable the family 10h processor mmconf while the RS780 mmconf is in use. -- Make strap programming more closely follow the reference BIOS. -- Disable PCIe bar 3 after using it. -- UMA size is no longer hardcoded. -- Disable write combining for all steppings to eliminate stability problem. -- Correct task file data. -- Improve the accuracy of the Atom table that passes information to the driver. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-23Remove the building warnings.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-22printk_foo -> printk(BIOS_FOO, ...)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16Features supported in RS780 code:Zheng Bao
* PCIe initialization. * Internal Graphics initialization. * HT Link initialization. It works in HT1 or HT3 mode. Note: 1. I tried to add the description of every step to the code. For example, if it is made based on rpr, section 2.4.5, I will pasted the words from 2.4.5 to the c code. But the document I worked with might be different with the most updated one. A new section has been added and the 2.4.5 might be changed to 2.5.5. That migh lead to confusing. I correct every comment if I met one. But I have to confess that I am so reluctant to find out everyone. I believe it will be correct in the long run. 2. The interanl graphics part is done by Libo Feng <libo.feng@amd.com>. 3. There is a conflict between RPR and our CIM code. Please see the comment in switching_gppsb_configurations in rs780_pcie.c. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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