coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2009-03-04	I just went on a bugfix frenzy and fixed all printk format warnings	Carl-Daniel Hailfinger
	triggered by the AMD 690/SB600 targets. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28	coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3	Stefan Reinauer
	a long time ago. This will make it easier to port v2 boards forward to v3 at some point (and other things) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-15	- Fix up amd pistachio and dbm690t.	Stefan Reinauer
	- make uma_memory_base and uma_memory_size uint64_t as they may be 64bit BARs on some platforms. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-23	Fix rs690 bug about GPPSB configuration.	Maggie Li
	Signed-off-by: Maggie Li <maggie.li@amd.com> Reviewed-by: Zheng Bao <Zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23	Handle RS690 quirks for 1 GHz noncoherent HyperTransport.	Carl-Daniel Hailfinger
	The RS690 chipset has a problem where it will not work with 1 GHz HT speed unless NB_CFG_Q_F1000_800 bit 0 is set. Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Bao, Zheng says: As a matter of fact, both 600Mhz and 1Ghz have their own specific setting. This patch has been tested on dbm690t which HT link works on 800Mhz. Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-17	Add 690G and 690(MT) internal graphics support.	Zheng Bao
	The device ID of 690G is 0x791E, while the ID of 690M and 690T is 0x791F This fixes booting on 690G. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-13	Move mainboard specific changes to the coreboot memory table into the	Stefan Reinauer
	mainboard specific code. (And add a hook to allow other mainboards do a similar thing if required) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01	Add AMD rs690 VID DID reporting and some minor cleanups.	Joe Bao
	Signed-off-by: Joe Bao <zheng.bao@amd.com> Reviewed-by: Maggie Li <maggie.li@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-13	Move AMD RS690 and SB600 PCI IDs to pci_ids.h where they should be.	Uwe Hermann
	Build-tested with the AMD dbm690t board. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-22	Patch for AMD RS690 chipset.	Michael Xie
	All the PCIe slots are enabled in this patch except power management. Signed-off-by: Michael Xie <Michael.Xie@amd.com> Reviewed-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1