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2017-11-30amd/{hudson,stoneyridge}: fix out of bounds readRichard Spiegel
southbridge/amd/pi/hudson/imc.c procedure enable_imc_thermal_zone was identified by coverity as having out of bounds access. Copies of the procedure are present in southbridge/amd/agesa/hudson/imc.c and in soc/amd/stoneyridge/imc.c. Fix the procedure in all 3 files. Fixes coverity CID 1260807: Out-of-bounds read. BUG=b:69835834 TEST=Build and platform boot to OS Change-Id: Ic16edc607358b9a688151735e6fcb3393d3bce80 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-28AMD platforms: Fix ASL comment that implies "\_SB" is southbridgeMartin Roth
Change-Id: I6ee86396a1c5aaee248a275b42da801cedace586 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-27smbus: Fix a typo ("Set the device I'm talking too")Jonathan Neuschäfer
Change-Id: Ia14bbdfe973cec4b366879cd2ed5602b43754260 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-20vboot: remove init_vbnv_cmos()Aaron Durbin
Instead of having each potential caller deal with the differences of cmos_init() and init_vbnv_cmos() when VBOOT is enabled put the correct logic within the callee, cmos_init(), for handling the vbnv in CMOS. The internal __cmos_init() routine returns when the CMOS area was cleared. BUG=b:63054105 Change-Id: Ia124bcd61d3ac03e899a4ecf3645fc4b7a558f03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21549 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-14device: acpi_name() should take a const struct deviceAaron Durbin
There's no reason to mutate the struct device when determining the ACPI name for a device. Adjust the function pointer signature and the respective implementations to use const struct device. Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-10amdfw: Clean up makefiles a bit moreMartin Roth
- Get rid of CONFIG_ prefix from variables that don't come from Kconfig. - Remove 2nd set of variables that are duplicates of the first set. - Delete duplicate set of Prerequisites Change-Id: I194b4c790b3e35353d480d34b60507a00f10ef11 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21451 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-25amd/XX/hudson: Remove #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)Kyösti Mälkki
Remove the unnecessary #if from around the #include "fchec.h". Turn #if statements into if(). Change-Id: Ia0582b3ce24c55dd439dfadb727507240accd9d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-25amd/pi/hudson: Fix FCH ECMartin Roth
Move the fchec.h files, which do not seem mainboard specific, out of the mainboard directories into the southbridge/soc directories. Change-Id: Idd271c6ab618aa4badf81c702212e7de35317021 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-25amd/pi/hudson: Move oem_fan_control()Martin Roth
It was not intentional to change oem_fan_control() to non-static with commit 23e5ba9 binarypi mainboards: Clean up IS_ENABLED fan control Every platform except bettong had its own static version of oem_fan_control, so remove the definition of oem_fan_control from imc.h, and move it out of imc.c into bettong's BiosCallOuts.c. Change-Id: Ie95ac1fd3a57259bb35796903aa8753ef0e70d70 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21189 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-24amd/pi/hudson: Clean up makefile.incMarc Jones
Sort makefile.inc into rom, ram, ver, smm stages and alphabetize. Change-Id: Ic8c6ca2b57527fcc96c135cc801a098201bf0465 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24amd/pi/hudson: Convert 48Mhz en to read/write32Marshall Dawson
Change-Id: I91e09757e5eea1eaf9b76921ad032ad2b79c14c5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-23AGESA binaryPI: Consolidate and fix sleep statesKyösti Mälkki
SSFG was meant to be used as a mask to enable sleep states _S1 thru _S4. However as a logical instead of bitwise 'and' operation was used, all the states were enabled if only one was marked available. State _S3 is now set conditionally if HAVE_ACPI_RESUME=y. For pi/hudson this had been fixed already preprocessor. Note that all boards had SSFG == 0x0D that previously enabled ACPI S3 sleep state even when it was not available. States _S1 and _S2 still appear enabled in ASL/AML but may not actually work. TEST: 'cat /sys/power/state' and notice choice 'mem' was removed from the list of available sleep states. Change-Id: I27d616871c1771f0c87d8fba23d4ce1569607765 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-07usbdebug: Refactor early enableKyösti Mälkki
Always sanity check for EHCI class device and move PCI function power enablement up. Change-Id: I1eebe813fbb420738af2d572178213fc660f392a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-07usbdebug: Consolidate EHCI_BAR setupKyösti Mälkki
There is assumption of static EHCI_BAR_INDEX, try to clean it up by bringing BAR programming at one spot. Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-04southbridge/pi/hudson: Fix GPIO bank1 control definitionMarshall Dawson
Change-Id: I3ef3ea3ea22faa0152d99923da2e57517ab3d0be Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-12binaryPI: Drop non-soc stoneyridge treesKyösti Mälkki
These sources are no longer part of build-tests and transition to soc/ appears to be completed. Change-Id: I9bc2212f44d79c795e5b8f6d62b6ee3c42de779a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-30southbridge/amd: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: I8fabb7331435eb518a5c95cb29c4ff5ca98560d2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-06-13Consolidate reset API, add generic reset_prepare mechanismJulius Werner
There are many good reasons why we may want to run some sort of generic callback before we're executing a reset. Unfortunateley, that is really hard right now: code that wants to reset simply calls the hard_reset() function (or one of its ill-differentiated cousins) which is directly implemented by a myriad of different mainboards, northbridges, SoCs, etc. More recent x86 SoCs have tried to solve the problem in their own little corner of soc/intel/common, but it's really something that would benefit all of coreboot. This patch expands the concept onto all boards: hard_reset() and friends get implemented in a generic location where they can run hooks before calling the platform-specific implementation that is now called do_hard_reset(). The existing Intel reset_prepare() gets generalized as soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now easily be added later if necessary). We will also use this central point to ensure all platforms flush their cache before reset, which is generally useful for all cases where we're trying to persist information in RAM across reboots (like the new persistent CBMEM console does). Also remove cpu_reset() completely since it's not used anywhere and doesn't seem very useful compared to the others. Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19789 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-11amd/pi: Add AMD fam16h TPM ACPI path supportPhilipp Deppenwiese
Change-Id: I5322d731a0dc655f2da14b87fa6cbc1e54b5abd5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/18522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-02amd/pi/hudson: Add config option for ACPI baseMarc Jones
Add a configuration option to assign the binaryPI base address for the ACPI registers. The binaryPI's assignment is determine at build time and no run-time configuration is allowed. Change-Id: Ida17022abfa6faceb0653c2cb87aacce4facef09 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19485 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-27amd/pi/hudson: Add VBNV cmos reset optionMarc Jones
If the mainboard supports VBNV, call init_vbnv_cmos() instead of the normal init_cmos(). The VBNV version does some VBNV pre and post setup around the normal init_cmos(). Change-Id: I34b02409019b945cd68c830e006e99338643f29c Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19399 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-27Revert "amd/pi/hudson: Move ACPI IO registers"Kyösti Mälkki
This reverts commit e7394ca90366d35ac52416c21052a3ceb459dc81. Configuration register for ACPI PM base address is initially configured inside the PI blob. Therefore, the value of HUDSON_ACPI_IO_BASE needs to be the same as DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS used in the build of binaryPI blob. Change-Id: I36700e49e21cc675e8e22b06efffb40e9c1e4236 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19454 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins)
2017-04-26amd/pi/hudson: Add TPM decode to SPI functionMarc Jones
Add a function to send the TPM decode to the SPI interface. Enables use of SPI TPMs on Hudson mainboards. Change-Id: I0e85ed92163e38eca6a55456708ab322d6a90d4c Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19402 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-26amd/pi/hudson: Clean up whitespace in header filesMarshall Dawson
Change spaces to tabs and do general whitespace cleanup. Change-Id: I4a4ecd42f91c9c6015a4f065b7386b17523ac6d9 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19401 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-26amd/pi/hudson: Move ACPI IO registersMarc Jones
Move the ACPI IO registers from 0x800 to 0x600 to avoid the IO space required by the Google EC, also at 0x800. This shouldn't have any conflicts on other AMD systems. Change-Id: Iac7388c15e899277fd506fb37965164488358335 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19171 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-26amd/pi/hudson: Add LPC IO decode enable functionMarc Jones
Add a function to enable LPC IO decode AKA WideIO. This can enable up to 3 regions, which may be 512 or 16 bytes wide. Change-Id: I2bed3a99180188101e00b4431d634227e488cbda Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19160 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-25amd/pi/hudson: Add GPIO get functionMarc Jones
Add a basic GPIO get function. Note that GPIO set, ACPI/GPE, and other features should come in future commits. Future changes to be modeled on the other soc/ gpio functions. Change-Id: I8f681865715ab947b525320a6f9fc63af1334b59 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19159 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-17sb/amd/pi/hudson: Spell verb in comment with a spacePaul Menzel
Change-Id: I7d0d8e2a20d15cbed30e98cf4468e9fb5dd0f1ad Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/19292 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-14amd/pi/hudson: Add SERIRQ setupMarc Jones
Enable SERIRQ in quiet or continuous mode based on Kconfig. Defaults to quite mode. Change-Id: Ib40a84719fcc3a5d6b3000c3c0412f1bcf629609 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19234 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-14amd/pi/hudson: Add hudson PM register definesMarc Jones
Clean up hudson PM register accesses with some register defines. Change-Id: I5ccf27a2463350baec53b7c79fe0fd4ec6c31306 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19233 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-06northbridge/amd/stoney: Add FT4 packageMarshall Dawson
Add package options to the CPU Kconfig that may be selected by the mainboard's Kconfig file. Stoney Ridge is available in FP4 and FT4 packages and each requires a unique binaryPI image. Default to the correct blob used by the northbridge by looking at the CPU's package. Also modify Gardenia to select the right package. See the Infrastructure Roadmap for FP4 (#53555) and FT4 (#55349) for additional details for the packages. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 7b8ed7b732b7cf5503862c5edc6537d672109aec) Change-Id: I7bb15bc4c85c5b4d3d5a6c926c4bc346a282ef27 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18989 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28amd/pi/hudson: Add fanless SMU firmware to buildMarshall Dawson
Use the new parameters in amdfwtool to include the additional SMU firmware into amdfw.rom. Change-Id: Ib44860780c8d5fb00c47f775a2a83b82ff3e1821 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19002 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28amd/pi/hudson: Reduce amdfw space requirementMarshall Dawson
Change the current implementation so that multiple PSP directory structures are not included, saving 448 KB. AMD created a mechanism so that multiple generations of APUs, in identical packages, may be supportable in one BIOS image. The PSP identifies the correct directory table by checking one of two pointers in the Embedded Firmware structure. Coreboot doesn't implement this capability, however it has been constructing amdfw.rom with two identical directory tables and two copies of each PSP blob. Tested on Bettong (Merlin Falcon / Carrizo) and Jadeite (Stoney). Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 11dfc3f621344db66d92b61d72927128ea48685f) Change-Id: I139f3bfdb319af803fef64e7bd848e95945f41aa Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18990 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28amd/pi/hudson: Add alternate method for including amdfwMarshall Dawson
For systems using Chrome OS, place the amdfw outside of cbfs control. The firmware must go to a fixed position at an offset of 0x20000 into the flash device. Potentially improve by adding a warning or error message for the condition when sizeof(amdfw) + sizeof(cbfs and metadata) > sizeof(flash). Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 2d9d631b39d7850576438a5b0979936bd33893e1) Change-Id: I38029bc03e5db260424cca293b1a7bceea4d0d75 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18435 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07amd/pi/hudson: Move APIC enable to CPU fileMarshall Dawson
Relocate the enabling of the LAPIC out of the southbridge source and surround it with a check for CONFIG_UDELAY_LAPIC (typical for AMD systems). The LAPIC is now enabled for all cores; not only the BSP, and not only when the UART is used. This solves the problem of APs not having their APICs enabled when the timer is expected to be functional, e.g. verstage often uses do_printk_va_list() instead of do_printk() which exits early for APs when CONFIG_SQUELCH_EARLY_SMP=y. The changes were tested with two Gardenia builds, one using verstage and another with CONFIG_SQUELCH_EARLY_SMP=n. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 93ffc311165f19d4192a5489051fa4264cd8e0ad) Change-Id: Ieaecc0bf921ee0d2691a8082f2431ea4d0c33749 Signed-off-by: Marc Jones <marcj303@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18436 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07amd/pi/hudson/acpi: Only declare S3 if it is supportedMarc Jones
Only declare S3 support in ACPI if CONFIG_HAVE_ACPI_RESUME is set. Change-Id: I6f8f62a92478f3db5de6feaa9822baad3f8e147e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18493 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07amd/pi/hudson: Add early SPI setupMarshall Dawson
Add some generic functions that can configure the SPI interface to have faster performance. Given that the hudson files are used across many generations of FCHs, make sure to refer to the appropriate BKDG or RRG before using the functions. Notable differences: * Hudson 1 defines read mode in CNTRL0 differently than later gens * Hudson 1 supports setting NormSpeed in Cntr1 but Hudson3 allows setting FastSpeed as well * Kabini, Mullins, Carrizo and Stoney Ridge contain a "new" SPI100 controller Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 1922d6f424dcf1f42e2f21fb7c6d53d7bcc247d0) Change-Id: Id12440e67bc575dbe4b980ef1da931d7bfae188d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18442 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07amd/pi/hudson: Add SPI definitions to headerMarshall Dawson
Add defines that will be used later for setting the fastest settings in the SPI controller. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 0d2c28b8156dcc1f3dc925b3c3ba15b6b07f202c) Change-Id: I660cc9ed6910c33042321c80453c7f74912455d9 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18441 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07amd/pi/hudson: Consolidate BITn definitionsMarshall Dawson
Remove unused definitions from a .c file and use the BIT(n) macro found in types.h instead. Convert existing definitions to BIT(n). Orignial-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit f403d12b49985ee9d9b339a6659b60ef1560519c) Change-Id: I24105bf75263236dbdbc2666f03033069d1d36d2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18440 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-01-10amd/hudson/pi: Fix position of hudson_fwmRicardo Ribalda Delgado
AMDFWTOOL calculates the location of the amdfw based on the CONFIG_ROM_SIZE. If HUDSON_FWM_POSITION does not match that location the resulting rom does not boot. This patch forces the position of HUDSON_FWM_POSITION to be the position calculated by amdfwrom. Tested on a Bettong derivative with a 16MiB flash. Change-Id: Id2ee96ee076293d48ade84fd6e976ca994dcf491 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/17925 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-12-19pcengines/apu2: add board supportPiotr Król
Initial work based on db-ft3b-ls and code released by Eltan. Board boots with some limitation. Now the AGESA binary is harcoded and board specific until it's fixed by the SoC vendor. memtest86+ from external repo skips looking for SPD on SMBus, which when performed cause memtest86+ to hang. Still didn't tried whole test suit. SeaBIOS 1.9.3 have some problems with USB which lead to no booting in some cases. Full log: https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872 SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios) works fine. Those changes are planned for upstream. Information about obtaining and booting Voyage Linux: https://github.com/pcengines/apu2-documentation#building-firmware-using-apu2-image-builder Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/14138 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-12-05mainboard & southbridge: Clear files that are just headersMartin Roth
These headers & comments indicating a lack of functionality don't help anything. We discourage copyrights and licenses on empty files, so just clear these. Change-Id: Id2ab060a2726cac6ab047d49a6e6b153f52ffe6d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17657 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-01AMD binaryPI: Use explicit PCI IO config access in bootblockKyösti Mälkki
This allows us to set MMCONF_SUPPORT_DEFAULT since we enable MMCONF early in romstage. Change-Id: I380cf483bfe4e2d64969110ae6d5d04c3ced2418 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17532 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-23AGESA binaryPI: Fix PCI ID namespaceKyösti Mälkki
The defines of device IDs reflects the vendor namespace the ID has been allocated from. Change-Id: Id98f45d5984752a9e8c0484d4cb94e93e55b12f6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17510 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-21AMD binaryPI: Drop commented code with bad PCI IDsKyösti Mälkki
There is mismatch of VENDOR_ID_AMD with DEVICE_ID_ATI, also the device IDs have not been defined. Change-Id: I3076cb08e3181e7f86de38deb18f1661f037bc38 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17508 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10southbridge/amd: Remove debug echo when building PIMartin Roth
If this information is needed, use make V=1. That will print the actual command, not a command that needs to be updated with every addition if it's going to stay in sync. Change-Id: I64d33d93c7fad3359d8ef78657bdb86d1fb4d4a1 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17328 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10southbridge/amd: update for amdfwtool size on command lineMartin Roth
amdfwtool was getting the ROM size as a #define when it was built. It has been updated to pass it in as a command line parameter, so now it can be built just once for abuild as a shared tool. Update the calls to amdfwtool to pass the ROM size. All platforms using amdfwtool had the output verified using a binary compare. This reverts commit 0529236ed22f1a28d29f2054674004c4f7a056e7 (Makefile.inc: Don't share amdfwtool between platforms) Change-Id: I188b34e08249f2d00bd48957ced750b21f1ec348 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17327 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-07southbridge/amd: Update Kconfig and makefiles for 00670F00Marc Jones
Add Stoney specific code subtree and fix Makefles and Kconfig files. Author: Charles Marslett <charles@scarlettechnologies.com> Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit c3a469d11e4676b3b63d11a30955113291d00ec8) Change-Id: Ic4d97a3745f7fc5a637ae6da17a9009b9757136e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17217 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07amd/pi/hudson: Move audio to northbridgeMarshall Dawson
Carrizo (00660F01), Merlin Falcon (00660F01), and Stoney Ridge (00670F00) locate the HD audio controller on the northbridge root complex at 9.2 instead of the FCH. This duplicates the existing ASL into the northbridge directories and reports the correct address. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit f68206c2b42c90076efd968a99f4d3a49e403438) Change-Id: I6d42bb40ad58c7f35e8c88ff27ebd327d656c021 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17216 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02amd/hudson: Add PSP2 build for combo BIOSMarc Jones
The Stoney processor can use multiple directory structures. Turn this feature on in the makefile. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit a3334632fd53c07a046c9b23161f6ee67e5cb16e) Change-Id: I40a9ef2e6bed51bc339d3f9ae7c6f316192c4a78 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17149 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
2016-11-02util/amdfwtool: Fix duplicate long option nameMarshall Dawson
Make the PSP2 smufirmware2 name unique so the command-line option gets picked up. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: <marcj303@gmail.com> (cherry picked from commit 98cf3880797f72aeb7169c3f8718a10092af9624) Change-Id: I5430cf8b81fb03c95e6ee9d7e53455e6224256ff Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17146 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-20southbridge/amd: Add space around operatorsElyes HAOUAS
Change-Id: I949ff7de072e5e0753d9c8ff0bf98abfca25798b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16637 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-13southbridge/amd/pi/hudson: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/amd/pi/hudson. Change-Id: I8b22a8d9f0e90afaf0f218c5c0924a78883b7498 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16475 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31src/southbridge: Code formatingElyes HAOUAS
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
These non-ascii & unprintable characters aren't needed. Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15977 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-31src/southbridge: Capitalize CPU, RAM and ROMElyes HAOUAS
Change-Id: I01413b9f8b77ecdcb781340f04c2fe9e24810264 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15941 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
This removes the newlines from all files found by the new int-015-final-newlines script. Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-09drivers/uart: Use uart_platform_refclk for all UART modelsLee Leahy
Allow the platform to override the input clock for the UART by implementing the routine uart_platform_refclk and setting the Kconfig value UART_OVERRIDE_REFCLK. Provide a default uart_platform_refclk routine which is disabled when UART_OVERRIDE_REFCLK is selected. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: If4afc45a828e5ba935fecb6d95b239625e912d14 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14612 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-03southbridge/amd: Drop HUDSON_FWM_INSIDE_CBFSPatrick Georgi
It's unused. Change-Id: I853702e40dcab9f193b2a3de7deeec80ab1d25f0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14568 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-07Correct some common spelling mistakesMartin Roth
- occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10ACPI: Fix IASL Warning about unused method for _OSI checkMartin Roth
According to the ACPI Spec for CondRefOf, the result argument is optional. In all of these locations, it was getting set but not used, creating a warning in new versions of IASL. Since it's an optional argument, just remove it. dsdt.aml 22: if(CondRefOf(\_OSI,Local1)) Warning 3144 - ^ Method Local is set but never used (Local1) Change-Id: I07f49ac5a3708838d1c4a7216dfb11acc415c881 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12692 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-09amdfwtool: Hide the prefix of targetZheng Bao
Make the definitions of rules compliant with others. Change-Id: Ieef3a9c3fae5beaa1ea3e14e890cfb9145090c3b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12685 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-09AMD/bettong: Add missing uart.c for UARTZheng Bao
Change-Id: Ie49732c6874f2b443e314eb3412ddee054d9c0bb Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12669 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08AMD/bettong: Remove the useless period (trivial)Zheng Bao
It seems that no one add period in Kconfig. Change-Id: Ie9c585a8e6f1a73036b92b2873dc19284d82dc39 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12668 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-11-24AMD/bettong: Add UART supportZheng Bao
The function delay in uart8250mem.c is not enough for hudson. I guess there are some problems in lapic_timer(). I uploaded a patch to gerrit to show the way to enable UART feature. http://review.coreboot.org/#/c/12343/4 Currently the HUDSON_UART is unchecked by default. Select HUDSON_UART to enable this feature. The UART is test at BIOS stage. Since it is not a standart UART device, the windows internal UART driver doesnt support it. I guess we need a driver to use it on windows. Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11749 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-20AMD Bettong: refactor PCI interrupt tableWANG Siyuan
1. Use write_pci_int_table to write registers 0xC00/0xC01. 2. Add GPIO, I2C and UART interrupt according "BKDG for AMD Family 15h Models 60h-6Fh Processors", 50742 Rev 3.01 - July 17, 2015 3. The interrupt valudes are moved from bettong/mptable.c. All devices work in Windows 10. Change-Id: Iad13bc02c84a5dfc7c24356436ac560f593304d7 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/11746 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-11-19AMD Hudson: Use amdfwtool to integrate firmwares.Zheng Bao
Change-Id: Ie17a744b6ef4e5405b3dfcecc1deb6462220ec60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12435 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-06amd binaryPI: Fix usbdebugKyösti Mälkki
EHCI functions have moved. Change-Id: I47e79d3790b272b0fc322d534de733889679622b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12264 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-30AMD Bettong: Fix usb device in devicetree for Carrizozbao
Add some missing devices to device tree and header. Remove the obsolete devices. Change-Id: Ieeca06c68fe8c8eef6be4fab43193b898aebf013 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11378 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-19AMD ROMSIG: Only check location if ROMSIG is usedMartin Roth
The location of the AMD ROMSIG binary was being checked and warnings were being printed even when the ROMSIG file wasn't being used. These false warnings are avoided by moving the warnings into the block where the CBFS file for the ROMSIG is generated. Change-Id: Ie44a2ad97ff3b15df6dc9b8166992de6ed837997 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11161 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-17AMD Binary PI: Fix the build when the user's group has a spaceDan Christensen
When the user's primary group contains a space ls -l and awk get the wrong value for the file size. This results in padding the coreboot_psp_directory_combine_pubkey.bin file too much which ultimately means RtmPubSigned.key can not be placed at the necessary offset. Changing from ls -l to ls -ln seemed like the most minimal, POSIX-friendly way to effect this change. Change-Id: Icbeaad476753924626adb6de53dc9a30052d91a6 Signed-off-by: Dan Christensen <opello@opello.org> Reviewed-on: http://review.coreboot.org/11242 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-08-09license headers: Drop FSF addresses againPatrick Georgi
Some FSF addresses found their way back into our tree. Change-Id: I34b465fc78734d818eca1d6962a1e62bf9d6e7f3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11145 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-30AMD binary PI: add southbridge support for fan controlWANG Siyuan
1. Add functions to support fan control. 2. When IMC firmware is added, the current firmwares' layout cause build error. There is not enough space to add some firmwares, so HUDSON_PSP_OFFSET is added to fix this problem. Change-Id: Ie470a88cb9da256d9f72ea56bf268c15df195784 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10720 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-21amd/hudson: Fix makefile FWM location checkMarc Jones
Fix typo. Use the correct math helper int-lt. Change-Id: Ia5e722020c75595dfcfb853ea8238fb8391f9a04 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10980 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-18amd/pi: Increase assumption for maximum CBFS file header sizePatrick Georgi
The new attributes increase the header size, breaking this assumption. Change-Id: Ib23862f27650b39133deafb74a24327b098b6e86 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10942 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-12southbridge/amd/pi/hudson: Fix HUDSON_DISABLE_IMC kconfig warningMartin Roth
Platforms selecting the HUDSON_DISABLE_IMC symbol were showing the warning: warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && CPU_AMD_AGESA_BINARY_PI) selects HUDSON_DISABLE_IMC which has unmet direct dependencies (SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN) By moving the definition of the symbol outside of the if block and removing the default n, we can get rid of the warning without changing the value for any platform. Change-Id: I5c1bdfbcf3c5c44ee05b8c5e679f6854d784d8dc Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10680 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2015-07-11amd/.../hudson: Warn if HUDSON_FWM_POSITION is not inside CBFSMartin Roth
Display a warning if CONFIG_HUDSON_FWM_POSITION is not inside CBFS. This can be extended to other Kconfig values for CBFS. Change-Id: I2423f7b361dda8aac5dab409fa7b656de486f635 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10683 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-11Calculate HUDSON_FWM_POSITION and display warning on mismatchMartin Roth
This patch calculates the address where the chipset firmware descriptor should be located and compares it against the actual value from Kconfig. If the two don't match, it puts up a warning. This could probably replace the config variable completely, but I wanted to see how other people felt before doing that. I seem to recall that the value used to be calculated, so I figure that there must be a reason it's done this way at this point. If we do want to keep the Kconfig setting, this patch could also be modified to just verify that the HUDSON_FWM_POSITION is inside the ROM space. Change-Id: I94addf463e2c694a94eef218ec855103a3bb5da5 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10682 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-25amd/pi/hudson: Fill ROMSIG with 0xFF instead of 0zbao
Besides the first five DWORDs, the offsets 0x40 & 0x41 are used to save SPI settings. They should only be 0xFF for being written. Other parts in ROMSIG are also changed to 0xFF for potential requirement. Change-Id: I61ea8295d5ee8ffbbd0cfcf9e4bece770d70e1f2 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/10651 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23AMD Kern: Fix path of PspSecureOs BLOBWANG Siyuan
AMD Kern uses PspSecureOs_prod_CZ.csbin rather than PspSecureOs_prod_CZ.sbin. PspSecureOs_prod_CZ.csbin is the firmware in CarrizoPI v1.0.0.7. Change-Id: Idf54ee808dd6965aec9b979be00b7f890a88b06d Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10639 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-13southbridge/amd/pi: Add support for new AMD southbridge KernWANG Siyuan
Kern is the southbridge of AMD Merlin Falcon(Carrizo). This add support of HD audio, lpc, sata and usb for Kern. Change-Id: Ie47e38bc1099cdb72002619cb1da269f3739678b Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10418 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-10AMD PI: remove unuseful ACPI codeWANG Siyuan
sata.asl and superio.asl are empty files. Remove them. Change-Id: Icd3e990aa713281e46dcbd8e0847166c77656b1c Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10505 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-08southbridge/amd/{agesa,pi}/hudson/lpc.c: Sync togetherEdward O'Callaghan
Resync together, backporting a fix for the initialization of 8254 and 8259, as in commit 8d9a1bd5. Also fix a typo and reduce out useless whitespace differences. Change-Id: I9a9b1fb9083c5417a8d061f90a89074f2a601ddf Signed-off-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reported-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10453 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-04devicetree: Discriminate device ops scan_bus()Kyösti Mälkki
Use of scan_static_bus() and tree traversals is somewhat convoluted. Start cleaning this up by assigning each path type with separate static scan_bus() function. For ME, SMBus and LPC paths a bus cannot expose bridges, as those would add to the number of encountered PCI buses. Change-Id: I8bb11450516faad4fa33b8f69bce5b9978ec75e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8534 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-05-26acpi: Remove monolithic ACPIVladimir Serbinenko
All boards now use per-device ACPI. This patch finishes migration by removing transitional kludges. Change-Id: Ie4577f89bf3bb17b310b7b0a84b2c54e404b1606 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7372 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-053rdparty: move to 3rdparty/blobsPatrick Georgi
There's now room for other repositories under 3rdparty. Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10109 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-053rdparty: Move to blobsPatrick Georgi
To move 3rdparty to 3rdparty/blobs (ie. below itself from git's broken perspective), we need to work around it - since some git implementations don't like the direct approach. Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-27kbuild: automatically include southbridgesStefan Reinauer
This change switches all southbridge vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in southbridge/Makefile.inc or in southbridge/<vendor>/Makefile.inc. In order to be able to drop southbridge/amd/Makefile.inc, some scattered source files had to be moved to a southbridge/amd/common directory, in accordance to what we are doing on other architectures already. This means, vendor and southbridge directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9796 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-02southbridge/amd/pi: Add initialization of 8254 and 8259Dave Frodin
This moves the initialization of the 8254 and 8259 out of the (unmerged) lamar mainboard romstage.c file and into the southbridge code as it is done in the other AMD southbridges. Change-Id: I73b375754ee4a9bf15981f2cd31056d7e04db23e Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/9182 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-04-01amd/pi/hudson: INCLUDES was renamed to CPPFLAGS_commonPatrick Georgi
And this path is already included properly elsewhere. Change-Id: I9fc6887fc047a9df1c4cb6fa4f841abb16f6d548 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9174 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-18bootstate: use structure pointers for scheduling callbacksAaron Durbin
The GCC 4.9.2 update showed that the boot_state_init_entry structures were being padded and assumed to be aligned in to an increased size. The bootstate scheduler for static entries, boot_state_schedule_static_entries(), was then calculating the wrong values within the array. To fix this just use a pointer to the boot_state_init_entry structure that needs to be scheduled. In addition to the previous issue noted above, the .bs_init section was sitting in the read only portion of the image while the fields within it need to be writable. Also, the boot_state_schedule_static_entries() was using symbol comparison to terminate a loop which in C can lead the compiler to always evaluate the loop at least once since the language spec indicates no 2 symbols can be the same value. Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8699 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-17southbridge/amd/pi: Enable early I/O decode to LPCDave Frodin
The decode of UART addresses down to the LPC bus needs to occur early to allow romstage console messages to be seen. This enables the decode of most of the I/O ports typically seen in a system. Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8661 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-11x86 SMM: Replace weak prototypes with weak function stubKyösti Mälkki
Change-Id: I682617cd2f4310d3e2e2ab6ffec51def28a4779c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7961 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-16acpi: Generate valid ACPI processor objectsTimothy Pearson
The existing code generated invalid ACPI processor objects if the core number was greater than 9. The first invalid object instance was autocorrected by Linux, but subsequent instances conflicted with each other, leading to a failure to boot if more than 10 CPU cores were installed. The modified code will function with up to 99 cores. Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8422 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-02-14southbridge/amd/pi: Combine and correct the IRQ text stringsDave Frodin
This combines the Avalon and Bolton tables of text descriptions of the IRQ assignments. It also corrects the text string for the SD controller on Bolton. Test: This was verified on amd/lamar. Change-Id: Ibc74641eb4e1f7581f26d260ba3d33201bcbf5e7 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8374 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-05southbridge/amd/pi: write_hpet requires additional config optionDave Frodin
This copies what was done in southbridge/amd/agesa in: commit 56f46d8 agesa/family15tn: Switch to per-device ACPI TEST: amd/lamar. Change-Id: Id8890ccd4a1ea783ad4740333ae6b061b6bbd7fc Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8288 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-05southbridge/amd/pi: Update Kconfig and makefiles for boltonDave Frodin
Change-Id: I208c931bdaee572c9df11b35c1e6e9f27609ea6c Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8287 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>