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path: root/src/southbridge/amd/pi/hudson/Makefile.inc
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2021-01-15build system: Always add coreboot.pre dependency to intermediatesPatrick Georgi
They all operate on that file, so just add it globally. Change-Id: I953975a4078d0f4a5ec0b6248f0dcedada69afb2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-15build system: Remove flock calls from intermediate processingPatrick Georgi
Now that intermediate coreboot.pre manipulation is serialized within the build system, remove the flock calls. Change-Id: I8a767918aec5fcb7127ebb19ac46e58bed7967fb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-14build system: Structure and serialize INTERMEDIATEPatrick Georgi
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying the file in some way. When running them in parallel, coreboot.pre can be read from and written to in parallel which can corrupt the result. Add a function to create those rules that also adds existing INTERMEDIATE targets to enforce an order (as established by evaluation order of Makefile.inc files). While at it, also add the addition to the PHONY target so we don't forget it. BUG=chromium:1154313, b:174585424 TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2 timeout and sercon) and saw that they were executed. Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08cbfstool: Use flock() when accessing CBFS filesJulius Werner
Trying to do multiple operations on the same CBFS image at the same time likely leads to data corruption. For this reason, add BSD advisory file locking (flock()) to cbfstool (and ifittool which is using the same file I/O library), so that only one process will operate on the same file at the same time and the others will wait in line. This should help resolve parallel build issues with the INTERMEDIATE target on certain platforms. Unfortunately, some platforms use the INTERMEDIATE target to do a direct dd into the CBFS image. This should generally be discouraged and future platforms should aim to clearly deliminate regions that need to be written directly by platform scripts with custom FMAP sections, so that they can be written with `cbfstool write`. For the time being, update the legacy platforms that do this with explicit calls to the `flock` utility. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I022468f6957415ae68a7a7e70428ae6f82d23b06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-22cpu/amd/pi: Remove unused cpu code 00660F01Martin Roth
Remove the processor directory and references to the Kconfig symbol. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I403a453362fd76d6ef2a5b75728a362efa4f2491 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-06amdfwtool: Use shell command to get depend file listZheng Bao
The amdfwtool is not available at the beginning of the building. So it may have error if it is missing. Change-Id: Id4db70986755cef8e98877c4e92841b25ced5452 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-04soc/amd: Change FIRMWARE_LOCATE to FIRMWARE_LOCATIONZheng Bao
Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30amdfwtool: Take a config file instead of command line parametersZheng Bao
To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-20soc/amd/picasso: Fix typo of Kconfig settingZheng Bao
USE_PSPSCUREOS -> USE_PSPSECUREOS. Change-Id: I5c89975cc317cb93e79509e885010d14a79dd7e1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-30Revert "amd/pi/hudson: Add GPIO get function"Kyösti Mälkki
This reverts commit dae95f0dfe9ad94922c940d3c0522d53284b4deb. There is filename conflict with top-level <gpio.h> and incompatibility with it. Only use was AMD_PI_KERN and we have no such platform in the tree anymore. Change-Id: I120b0bfda1501e9941c71315852d87d251f76a5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42743 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCKKyösti Mälkki
Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37440 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16soc/amd,{agesa,pi}/hudson: Have do_board_reset in all stagesKyösti Mälkki
Change-Id: I38a721c359ab7761c5a3ea79da0c159fd7f58970 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37711 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-04sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initializationMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Reviewed-on: https://review.coreboot.org/c/coreboot/+/37168 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-18*/Makefile: Always build enable_usbdebug.cArthur Heymans
This always builds the usb debug callback functions when implemented. They get garbage collected if CONFIG_USBDEBUG is not set. Change-Id: I33051df583645cd00d08e06774383763172d5822 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-17binaryPI: Drop PSP Secure OS from buildKyösti Mälkki
For pcengines/apu2 variants we do not even send DRAM ready message to PSP. Possibly some GFX/DRM depends of running PSP but these devices are headless. And we don't support fTPM inside PSP either. Reduces blob footprint in SPI from 466 KiB to 234KiB. Change-Id: I803722171cba9b3601fb0b4a2c0e984566f435ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-09-17binaryPI: Move Hudson firmware higher in CBFSKyösti Mälkki
Move it above 'AGESA' to increase the maximum continuous free space in CBFS from 5.3 MiB to 5.8 MiB. Also fixes build for cases where CBFS_SIZE < ROM_SIZE, thus allowing FMAP regions. NOTE: Due to off-by-one error in binaryPI, offset 0xFFFA0000 that amdfwtool advertises fails for xHCI firmware loading. Change-Id: Ic78520f4248f0943769e66a8825911c0ddcc368c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-09-17binaryPI: Refactor Makefile for PSP directoryKyösti Mälkki
Change-Id: I3c2d528519ac26b24159a46400f232d6acd629e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-07-09arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-06usbdebug: Make the EHCI debug console work in the bootblockArthur Heymans
Currently this needlessly initializes the hardware in the both the romstage and the bootblock, but it works. Build option is renamed to USBDEBUG_IN_PRE_RAM to reflect the use better, related support files can be built to pre-ram stages regardless of usbdebug being enabled or not. Tested on Google/peppy (adapted to C_ENVIRONMENT_BOOTBLOCK). Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-10amdfw: Clean up makefiles a bit moreMartin Roth
- Get rid of CONFIG_ prefix from variables that don't come from Kconfig. - Remove 2nd set of variables that are duplicates of the first set. - Delete duplicate set of Prerequisites Change-Id: I194b4c790b3e35353d480d34b60507a00f10ef11 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21451 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-24amd/pi/hudson: Clean up makefile.incMarc Jones
Sort makefile.inc into rom, ram, ver, smm stages and alphabetize. Change-Id: Ic8c6ca2b57527fcc96c135cc801a098201bf0465 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-12binaryPI: Drop non-soc stoneyridge treesKyösti Mälkki
These sources are no longer part of build-tests and transition to soc/ appears to be completed. Change-Id: I9bc2212f44d79c795e5b8f6d62b6ee3c42de779a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-04-25amd/pi/hudson: Add GPIO get functionMarc Jones
Add a basic GPIO get function. Note that GPIO set, ACPI/GPE, and other features should come in future commits. Future changes to be modeled on the other soc/ gpio functions. Change-Id: I8f681865715ab947b525320a6f9fc63af1334b59 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19159 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-06northbridge/amd/stoney: Add FT4 packageMarshall Dawson
Add package options to the CPU Kconfig that may be selected by the mainboard's Kconfig file. Stoney Ridge is available in FP4 and FT4 packages and each requires a unique binaryPI image. Default to the correct blob used by the northbridge by looking at the CPU's package. Also modify Gardenia to select the right package. See the Infrastructure Roadmap for FP4 (#53555) and FT4 (#55349) for additional details for the packages. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 7b8ed7b732b7cf5503862c5edc6537d672109aec) Change-Id: I7bb15bc4c85c5b4d3d5a6c926c4bc346a282ef27 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18989 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28amd/pi/hudson: Add fanless SMU firmware to buildMarshall Dawson
Use the new parameters in amdfwtool to include the additional SMU firmware into amdfw.rom. Change-Id: Ib44860780c8d5fb00c47f775a2a83b82ff3e1821 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19002 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28amd/pi/hudson: Reduce amdfw space requirementMarshall Dawson
Change the current implementation so that multiple PSP directory structures are not included, saving 448 KB. AMD created a mechanism so that multiple generations of APUs, in identical packages, may be supportable in one BIOS image. The PSP identifies the correct directory table by checking one of two pointers in the Embedded Firmware structure. Coreboot doesn't implement this capability, however it has been constructing amdfw.rom with two identical directory tables and two copies of each PSP blob. Tested on Bettong (Merlin Falcon / Carrizo) and Jadeite (Stoney). Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 11dfc3f621344db66d92b61d72927128ea48685f) Change-Id: I139f3bfdb319af803fef64e7bd848e95945f41aa Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18990 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28amd/pi/hudson: Add alternate method for including amdfwMarshall Dawson
For systems using Chrome OS, place the amdfw outside of cbfs control. The firmware must go to a fixed position at an offset of 0x20000 into the flash device. Potentially improve by adding a warning or error message for the condition when sizeof(amdfw) + sizeof(cbfs and metadata) > sizeof(flash). Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 2d9d631b39d7850576438a5b0979936bd33893e1) Change-Id: I38029bc03e5db260424cca293b1a7bceea4d0d75 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18435 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-10amd/hudson/pi: Fix position of hudson_fwmRicardo Ribalda Delgado
AMDFWTOOL calculates the location of the amdfw based on the CONFIG_ROM_SIZE. If HUDSON_FWM_POSITION does not match that location the resulting rom does not boot. This patch forces the position of HUDSON_FWM_POSITION to be the position calculated by amdfwrom. Tested on a Bettong derivative with a 16MiB flash. Change-Id: Id2ee96ee076293d48ade84fd6e976ca994dcf491 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/17925 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10southbridge/amd: Remove debug echo when building PIMartin Roth
If this information is needed, use make V=1. That will print the actual command, not a command that needs to be updated with every addition if it's going to stay in sync. Change-Id: I64d33d93c7fad3359d8ef78657bdb86d1fb4d4a1 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17328 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10southbridge/amd: update for amdfwtool size on command lineMartin Roth
amdfwtool was getting the ROM size as a #define when it was built. It has been updated to pass it in as a command line parameter, so now it can be built just once for abuild as a shared tool. Update the calls to amdfwtool to pass the ROM size. All platforms using amdfwtool had the output verified using a binary compare. This reverts commit 0529236ed22f1a28d29f2054674004c4f7a056e7 (Makefile.inc: Don't share amdfwtool between platforms) Change-Id: I188b34e08249f2d00bd48957ced750b21f1ec348 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17327 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-07southbridge/amd: Update Kconfig and makefiles for 00670F00Marc Jones
Add Stoney specific code subtree and fix Makefles and Kconfig files. Author: Charles Marslett <charles@scarlettechnologies.com> Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit c3a469d11e4676b3b63d11a30955113291d00ec8) Change-Id: Ic4d97a3745f7fc5a637ae6da17a9009b9757136e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17217 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02amd/hudson: Add PSP2 build for combo BIOSMarc Jones
The Stoney processor can use multiple directory structures. Turn this feature on in the makefile. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit a3334632fd53c07a046c9b23161f6ee67e5cb16e) Change-Id: I40a9ef2e6bed51bc339d3f9ae7c6f316192c4a78 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17149 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
2016-11-02util/amdfwtool: Fix duplicate long option nameMarshall Dawson
Make the PSP2 smufirmware2 name unique so the command-line option gets picked up. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: <marcj303@gmail.com> (cherry picked from commit 98cf3880797f72aeb7169c3f8718a10092af9624) Change-Id: I5430cf8b81fb03c95e6ee9d7e53455e6224256ff Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17146 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-03southbridge/amd: Drop HUDSON_FWM_INSIDE_CBFSPatrick Georgi
It's unused. Change-Id: I853702e40dcab9f193b2a3de7deeec80ab1d25f0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14568 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-09amdfwtool: Hide the prefix of targetZheng Bao
Make the definitions of rules compliant with others. Change-Id: Ieef3a9c3fae5beaa1ea3e14e890cfb9145090c3b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12685 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-24AMD/bettong: Add UART supportZheng Bao
The function delay in uart8250mem.c is not enough for hudson. I guess there are some problems in lapic_timer(). I uploaded a patch to gerrit to show the way to enable UART feature. http://review.coreboot.org/#/c/12343/4 Currently the HUDSON_UART is unchecked by default. Select HUDSON_UART to enable this feature. The UART is test at BIOS stage. Since it is not a standart UART device, the windows internal UART driver doesnt support it. I guess we need a driver to use it on windows. Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11749 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-19AMD Hudson: Use amdfwtool to integrate firmwares.Zheng Bao
Change-Id: Ie17a744b6ef4e5405b3dfcecc1deb6462220ec60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12435 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-19AMD ROMSIG: Only check location if ROMSIG is usedMartin Roth
The location of the AMD ROMSIG binary was being checked and warnings were being printed even when the ROMSIG file wasn't being used. These false warnings are avoided by moving the warnings into the block where the CBFS file for the ROMSIG is generated. Change-Id: Ie44a2ad97ff3b15df6dc9b8166992de6ed837997 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11161 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-17AMD Binary PI: Fix the build when the user's group has a spaceDan Christensen
When the user's primary group contains a space ls -l and awk get the wrong value for the file size. This results in padding the coreboot_psp_directory_combine_pubkey.bin file too much which ultimately means RtmPubSigned.key can not be placed at the necessary offset. Changing from ls -l to ls -ln seemed like the most minimal, POSIX-friendly way to effect this change. Change-Id: Icbeaad476753924626adb6de53dc9a30052d91a6 Signed-off-by: Dan Christensen <opello@opello.org> Reviewed-on: http://review.coreboot.org/11242 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-30AMD binary PI: add southbridge support for fan controlWANG Siyuan
1. Add functions to support fan control. 2. When IMC firmware is added, the current firmwares' layout cause build error. There is not enough space to add some firmwares, so HUDSON_PSP_OFFSET is added to fix this problem. Change-Id: Ie470a88cb9da256d9f72ea56bf268c15df195784 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10720 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-21amd/hudson: Fix makefile FWM location checkMarc Jones
Fix typo. Use the correct math helper int-lt. Change-Id: Ia5e722020c75595dfcfb853ea8238fb8391f9a04 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10980 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-18amd/pi: Increase assumption for maximum CBFS file header sizePatrick Georgi
The new attributes increase the header size, breaking this assumption. Change-Id: Ib23862f27650b39133deafb74a24327b098b6e86 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10942 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-11amd/.../hudson: Warn if HUDSON_FWM_POSITION is not inside CBFSMartin Roth
Display a warning if CONFIG_HUDSON_FWM_POSITION is not inside CBFS. This can be extended to other Kconfig values for CBFS. Change-Id: I2423f7b361dda8aac5dab409fa7b656de486f635 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10683 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-11Calculate HUDSON_FWM_POSITION and display warning on mismatchMartin Roth
This patch calculates the address where the chipset firmware descriptor should be located and compares it against the actual value from Kconfig. If the two don't match, it puts up a warning. This could probably replace the config variable completely, but I wanted to see how other people felt before doing that. I seem to recall that the value used to be calculated, so I figure that there must be a reason it's done this way at this point. If we do want to keep the Kconfig setting, this patch could also be modified to just verify that the HUDSON_FWM_POSITION is inside the ROM space. Change-Id: I94addf463e2c694a94eef218ec855103a3bb5da5 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10682 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-25amd/pi/hudson: Fill ROMSIG with 0xFF instead of 0zbao
Besides the first five DWORDs, the offsets 0x40 & 0x41 are used to save SPI settings. They should only be 0xFF for being written. Other parts in ROMSIG are also changed to 0xFF for potential requirement. Change-Id: I61ea8295d5ee8ffbbd0cfcf9e4bece770d70e1f2 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/10651 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23AMD Kern: Fix path of PspSecureOs BLOBWANG Siyuan
AMD Kern uses PspSecureOs_prod_CZ.csbin rather than PspSecureOs_prod_CZ.sbin. PspSecureOs_prod_CZ.csbin is the firmware in CarrizoPI v1.0.0.7. Change-Id: Idf54ee808dd6965aec9b979be00b7f890a88b06d Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10639 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-13southbridge/amd/pi: Add support for new AMD southbridge KernWANG Siyuan
Kern is the southbridge of AMD Merlin Falcon(Carrizo). This add support of HD audio, lpc, sata and usb for Kern. Change-Id: Ie47e38bc1099cdb72002619cb1da269f3739678b Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10418 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-053rdparty: move to 3rdparty/blobsPatrick Georgi
There's now room for other repositories under 3rdparty. Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10109 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-053rdparty: Move to blobsPatrick Georgi
To move 3rdparty to 3rdparty/blobs (ie. below itself from git's broken perspective), we need to work around it - since some git implementations don't like the direct approach. Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-01amd/pi/hudson: INCLUDES was renamed to CPPFLAGS_commonPatrick Georgi
And this path is already included properly elsewhere. Change-Id: I9fc6887fc047a9df1c4cb6fa4f841abb16f6d548 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9174 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27southbridge/amd/pi: Rename Avalon to HudsonDave Frodin
To maintain consistancy with southbridge/amd/agesa/hudson rename pi/avalon to pi/hudson in advance of adding support for the base hudson southbridge. Change-Id: Icff8c4c06aae2d40cbd9e90903754735ac3510c3 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8251 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-23 22:02:19 +0000