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2014-12-16Drop GX1, CS5330 and related boardsStefan Reinauer
There is no Cache As Ram for these boards, let's get rid of them. Change-Id: Ib41f8cd64fc9a440838aea86076d6514aacb301c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7117 Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2008-01-18Please bear with me - another rename checkin. This qualifies as trivial, noStefan Reinauer
code is changed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-14This is a full rewrite of all the CS5530/CS5530A code. The previous code wasUwe Hermann
mostly undocumented, had a broken coding style, contained lots of dead code and had several other problems, e.g. it enabled write access to the ROM (why?), it unconditionally enabled primary/secondary IDE (which should have a config option) and that even _twice_ (which is um... wrong). The new code - has 'ide0_enable' and 'ide1_enable' config options (which actually work) to enable/disable the primary/secondary IDE interface in Config.lb. - Does _not_ enable write access to the ROM (or is there some good reason to do that? If so, it should at least have a config option). - Contains a bit more documentation. - Uses readable (and documented) #defines instead of hardcoded magic values. - aaand... it actually compiles ;-) Yep, that's right. The previous code wouldn't even build, as it hadn't been fully ported from v1 (still used v1 functions which are simply not available in v2). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-26arch import user (historical)
Creator: Hamish Guthrie <hamish@prodigi.ch> Added AMD GX1 northbridge and cs5530 Southbridge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1