| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-03-01 | device/pci: Fix PCI accessor headers | Kyösti Mälkki |
| 2019-01-14 | AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON | Kyösti Mälkki |
| 2018-10-31 | reset: Finalize move to new API | Nico Huber |
| 2018-07-09 | src/southbridge: Use "foo *bar" instead of "foo* bar" | Elyes HAOUAS |
| 2018-05-20 | sb/amd/common: Get rid of device_t | Elyes HAOUAS |
| 2018-01-24 | AGESA f15 cimx/sb700: Remove unused chips code | Kyösti Mälkki |
| 2017-08-23 | AGESA binaryPI: Consolidate and fix sleep states | Kyösti Mälkki |
| 2017-01-05 | src/amd: Add common definition of AMD ACPI MMIO address | Timothy Pearson |
| 2016-08-31 | src/southbridge: Code formating | Elyes HAOUAS |
| 2015-11-20 | southbridge/amd: add support for Bolton FCH | Felix Held |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-06-13 | southbridge/amd/pi: Add support for new AMD southbridge Kern | WANG Siyuan |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-04-27 | kbuild: automatically include southbridges | Stefan Reinauer |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |